B69000 Asiliant Technologies, B69000 Datasheet - Page 314

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Clock Generation
B-1
Appendix B
Clock Generation
Clock Synthesizer
The graphics controller contains two complete phase-locked loops (PLLs) to synthesize the internal Dot
Clock (DCLK) and Memory Clock (MCLK) from an externally supplied reference frequency. Each of the two
clock synthesizer phase lock loops may be programmed to output frequencies ranging between 3MHz and
the maximum specified operating frequency for that clock in increments not exceeding 0.5%. An external
crystal-controlled oscillator (TTL) generates the reference frequency of 14.31818 MHz that is driven into the
graphics controller on pin C3. The graphics controller can not generate the 14.31818 MHz reference
frequency using only an external crystal.
Dot Clock (DCLK)
The dot clock is used as the basis for all display timing. The horizontal and vertical sync frequencies are
derived by dividing down the dot clock.
In borrowing from VGA parlance, there are said to be three dot clocks: DCLK0, DCLK1 and DCLK2. In
truth, there is actually only a single PLL, but it can be configured with divisor values from any one of three
sets of registers within the XRC0-XRCF group of registers, and these three groups of registers are referred
to as if they were DCLK0, DCLK1 and DCLK2. Bits 3 and 2 of the Miscellaneous Output Register (MSR)
are used to select which one of these 3 sets of registers will be used to supply the divisor values that the
PLL will use in creating the dot clock at any given time.
During reset, the first two sets of these registers (DCLK0 and DCLK1) default to values that specify the two
standard VGA dot clocks of 25.175MHz and 28.322MHz, and normally the values in these first two sets of
registers are not changed. The third set of registers (DCLK2) is used for all modes that are not of the VGA
standard, i.e., the extended modes.
Memory Clock (MCLK)
The memory clock is used as the basis for all memory timing. It is normally set once following hardware
reset, and is not normally modified again.
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69000 Databook
Subject to Change Without Notice
Revision 1.3 8/31/98