B69000 Asiliant Technologies, B69000 Datasheet - Page 155
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B69000
Manufacturer Part Number
B69000
Description
Manufacturer
Asiliant Technologies
Datasheet
1.B69000.pdf
(360 pages)
Specifications of B69000
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12-2
ARX
read/write at I/O address 3C0h
Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,”
“color plane,” “display memory plane,” and “memory map” have been all been used in IBM
VGA standard to describe the four separate regions in the frame buffer where the pixel color or attribute
information is split up and stored in standard VGA planar modes. This use of multiple terms for the same
subject was deemed to be confusing, therefore AR12 is called the Memory Plane Enable Register.
7-6
5
4-0
AR00-AR0F
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 00h to 0Fh
Note: Bits 3 and 2 of the Color Select Register (AR14) supply bits P7 and P6 for the values contained in
all 16 of these registers. Bits 1 and 0 of the Color Select Register (AR14) can also replace bits P5 and P4
for the values contained in all 16 of these registers if bit 7 of the Mode Control Register (AR10) is set to 1.
7-6
5-0
&+,36
7
7
Reserved
Video Enable
Attribute Controller Register Index
Reserved
Palette Bits P5-P0
Reserved
Reserved
69000 Databook
Attribute Controller Index Register
0: Disables video, allowing the attribute controller color registers (AR00-AR0F) to be
accessed by the CPU.
1: Enables video, causing the attribute controller color registers (AR00-AR0F) to be
rendered inaccessible by the CPU.
Note: In the VGA standard, this is called the “Palette Address Source” bit.
These five bits are used to select any one of the attribute controller registers, AR00 through
AR14, to be accessed.
In each of these 16 registers, these are the lower 6 of 8 bits that are used to map either text
attributes or pixel color input values (for modes that use 16 colors) to the 256 possible
colors available to be selected in the palette.
6
6
Palette Registers 0-F
Enable
Video
5
5
Subject to Change Without Notice
Attribute Controller Registers
4
4
Attribute Controller Register Index
Palette Bits P5-P0
3
3
2
2
Revision 1.3 8/31/98
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