B69000 Asiliant Technologies, B69000 Datasheet - Page 231

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-16
FR12
read/write at I/O address 3D1h with index at I/O address 3D0h set to 12h
7-6
5
4
&+,36
7
FP Data Width
FP Data Width
Force FP Data Signals High during Vertical Blank
0: Flat panel data output signals are not forced high during vertical blanking.
1: Flat panel data output signals are forced high during vertical blanking.
Force FP HSync (LP) during Vertical Blank
0: FP Display Enable output is generated by inverting both FP Vertical and Horizontal Blank
therefore FP Display Enable will not toggle active during Vertical Blank time. FP HSync (LP) is not
generated during Vertical Blank except when bit 3 is set to 1. This is the default after reset.
1: FP Display Enable output is generated by inverting FP Horizontal Blank only therefore FP
Display Enable will be active during Vertical Blank time. FP HSync (LP) will also be active during
Vertical Blank.
This bit should be set only for SS panels which require FP HSync (LP) to be active during vertical
blank time when bit 3 is 0. This bit should be reset when using DD panels or when bit 3 is 1.
69000 Databook
FP Format 2 Register
6
Bits
7 6
0 0
0 1
1 0
1 1
16-bit panel data width. For color TFT panel this is the 565
RGB interface. This is the default after reset.
24-bit panel data width. For color the TFT panel this is the
888 RGB interface. This setting can also be used for the 24-
bit color STN-DD panel.
Reserved.
36-bit panel data width (TFT panels only). Program 000 in
shift clock divide bits of FR10.
Data High
Force FP
5
Subject to Change Without Notice
Flat Panel Registers
HSYNC
Force
4
FP Data Width
FP Blank#
Select
3
Clk Mask
STN-DD
2
Clock Mask
Revision 1.3 8/31/98
1
Clock Divide
0