B69000 Asiliant Technologies, B69000 Datasheet - Page 250

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR48
read/write at I/O address 3D1h with index at I/O address 3D0h set to 48h
When the FP Display engine is enabled (when FR01 bit 1 is set to 1), it uses this register.
7-5
4
3
2
1
0
&+,36
7
Reserved (R/W) (reset state: 0)
Enable Text Mode Vertical Stretching (ETVS)
0: Disable vertical stretching (default)
1: Enable vertical stretching
Text Mode Vertical Stretching Priority
0: Priority: ETVS, EVLR (default)
1: Priority: EVLR, ETVS
This bit is effective in text modes if bits 2 and 4 are set.
Enable Vertical Line Replication (EVLR)
0: Disables vertical line replication (default)
1: Enables vertical line replication
This bit is effective in both text and graphics modes.
Enable Vertical Centering
0: Disables vertical centering (default)
1: Enables vertical centering
This bit is effective only when bit 0 is "1".
Enable Vertical Compensation (EVCP)
0: Disables vertical compensation feature (default)
1: Enables vertical compensation feature
69000 Databook
Reserved (R/W)
Vertical Compensation Register
(000)
6
5
Subject to Change Without Notice
Flat Panel Registers
ETVS
(0)
4
Text Mode
Stretch
(0)
3
EVLR
(0)
2
Centering
Vertical
(0)
Revision 1.3 8/31/98
1
EVCP
(0)
0
15-35