B69000 Asiliant Technologies, B69000 Datasheet - Page 29

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PCI/AGP Bus Interface
Note:
driven high for one clock before released, and are not driven for at least one cycle after being released by
the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between
transactions.
&+,36
K4
L1
BGA mBGA
M1
K2
K1
PIN
D2
C1
S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are
PIN
E4
C1
H3
H1
69000 Databook
H2 TRDY#
J2
J1 STOP#
Pin Name
RESET#
BUSCLK
PAR
FRAME#
IRDY#
Type
S/TS
S/TS
I/O
In
In
In
In
Subject to Change Without Notice
Active
High
High
Low
Low
Low
Low
Low
Pin Descriptions
Powered Description
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Reset. This input sets all signals and registers in
the chip to a known state. All outputs from the chip
are tri-stated or driven to an inactive state. This pin
is ignored during Standby mode (STNDBY# pin
low). The remainder of the system (therefore
the system bus) may be powered down if
desired (all bus output pins are tri-stated in
Standby mode).
Bus Clock. This input provides the timing reference
for all PCI and AGP bus transactions. All bus inputs
except RESET# are sampled on the rising edge of
BCLK. BCLK may be any frequency from DC up to
33MHz for PCI, or up to 66MHz for AGP.
Parity. This signal is used to maintain even parity
across AD0-31 and C/BE0-3#. PAR is stable and
valid one clock after the address phase. For data
phases PAR is stable and valid one clock after
either IRDY# is asserted on a write transaction or
TRDY# is asserted on a read transaction. Once
PAR is valid, it remains valid until one clock after the
completion of the current data phase (i.e., PAR has
the same timing as AD0-31 but delayed by one
clock). The bus master drives PAR for address and
write data phases; the target drives PAR for read
data phases.
Cycle Frame. Driven by the current master to
indicate the beginning and duration of an access.
Assertion indicates a bus transaction is beginning
(while asserted, data transfers continue); de-
assertion indicates the transaction is in the final
data phase
Initiator Ready. Indicates the bus master's ability to
complete the current data phase of the transaction.
During a write, IRDY# indicates valid data is present
on AD0-31; during a read it indicates the master is
prepared to accept data. A data phase is completed
on any clock when both IRDY# and TRDY# are
sampled then asserted (wait cycles are inserted
until this occurs).
Target Ready. Indicates the target's ability to
complete the current data phase of the transaction.
During a read, TRDY# indicates that valid data is
present on AD0-31; during a write it indicates the
target is prepared to accept data. A data phase is
completed on any clock when both IRDY# and
TRDY# are sampled then asserted (wait cycles are
inserted until this occurs).
Stop. Indicates the current target is requesting the
master to stop the current transaction.
Revision 1.3 8/31/98
2-5