B69000 Asiliant Technologies, B69000 Datasheet - Page 158

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

AR12
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 12h
Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,”
“color plane,” “display memory plane,” and “memory map” have been all been used in IBM
VGA standard to describe the 4 separate regions in the frame buffer that are amongst which pixel color or
attributes information is split up and stored in standard VGA planar modes. This use of multiple terms for
the same subject was deemed to be confusing, therefore AR12 is called the Memory Plane Enable Register.
7-6
5-4
Note: These bits are largely unused by current software. They are provided for EGA compatibility.
3-0
&+,36
7
Reserved
Video Status Mux
Enable Plane 3-0
Reserved
69000 Databook
Memory Plane Enable Register
These 2 bits are used to select 2 of the 8 possible palette bits (P7-P0) to be made available
to be read via bits 5 and 4 of the Input Status Register 1 (ST01). The table below shows
the possible choices.
These 4 bits individually enable the use of each of the 4 memory planes in providing 1 of
the 4 bits used in video output to select 1 of 16 possible colors from the palette to be
displayed.
0: Disables the use of the corresponding memory plane in video output to select colors,
forcing the bit that the corresponding memory plane would have provided to a value of 0.
1: Enables the use of the corresponding memory plane in video output to select colors.
6
Video Status Mux
5
Subject to Change Without Notice
Attribute Controller Registers
AR12 Bit
5 4
0 0
0 1
1 0
1 1
4
Plane 3
Enable
ST01 Bit
P2 P0
P5 P4
P3 P1
P7 P6
5
3
4
Plane 2
Enable
2
Plane 1
Enable
Revision 1.3 8/31/98
1
®
literature on the
Plane 0
Enable
0
12-5