B69000 Asiliant Technologies, B69000 Datasheet - Page 321

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B-8
Clock Generation
STN-DD Panel Buffering
STN-DD panels require the upper and lower halves of the panel to be refreshed simultaneously. In addition,
Temporal Modulated Energy Distribution (TMED) or Frame Rate Control (FRC) is needed to achieve more
than 8 colors, since the panel itself supports only 3 bits per pixel (one bit each for red, green, and blue). The
69000 implements STN-DD support using either a full frame buffer or a half frame buffer (programmable
option). The buffer holds three bits per pixel, packed in groups of 10 pixels per DWORD. Thus, the buffer
requires 0.4 bytes per pixel in addition to the main display memory.
The half frame buffer operates as follows. As each pixel is read out of display memory, the appropriate 3-
bit code for the panel is calculated and sent to the panel. In addition, the proper 3-bit code for the same
pixel in the NEXT frame is also calculated, with allowance for frame rate control. The second 3-bit code is
written into the half frame buffer. During this same pixel time, the previously stored 3-bit code is read out
of the half frame buffer and sent to the other half of the panel.
The full frame buffer operates in a similar manner. As each two pixels are read out of display memory, the
appropriate 3-bit codes for the panel are calculated and stored in the buffer. During the same two pixel
times, previously stored 3-bit codes are read out of the buffer and sent to upper and lower halves of the
panel.
There is no difference between a half frame buffer and a full frame buffer in the effect on display memory
bandwidth. Both options require 0.4 bytes per pixel to be read and written during each pixel time. If the
buffer is located in main display memory, the total effect is 0.8 extra bytes of memory access per pixel
(regardless of pixel depth). In 16 bpp modes, a total of 2.8 bytes of memory access must be performed per
pixel – 2 bytes for the 16 original pixel bits, plus 0.8 byte for the buffer bits. The graphics controller actually
reads and writes one DWORD in the buffer for every 10 pixels, which is the same as 0.8 bytes per pixel.
For mode support calculations, it is usually best to assume 1.0 byte per pixel instead of 0.8, since the RAS
overhead for STN-DD buffer accesses is somewhat higher than for normal pixel accesses due to shorter
DRAM bursts.
The half frame buffer has a timing characteristic for the panel that may be either a problem or an advantage,
depending on the application. The panel is refreshed at twice the pixel rate imposed on the display memory.
In simultaneous CRT and panel mode, this means that the pixel rate is dictated by the CRT requirements,
and the panel is refreshed at twice that rate. This may exceed panel timing limitations. However, in panel-
only mode, the pixel rate from display memory can be reduced to half of what a CRT would need, which
imposes half the burden on display memory bandwidth and allows more complex video modes to be
supported by the available display memory bandwidth.
The full frame buffer allows the panel refresh rate to be the same as the CRT in simultaneous display mode,
but requires the buffer size to be twice as large (full frame instead of half frame, though only 0.4 bytes per
pixel).
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69000 Databook
Subject to Change Without Notice
Revision 1.3 8/31/98