B69000 Asiliant Technologies, B69000 Datasheet - Page 317

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B-4
Programming Constraints
The programmer must be aware of the following five programming constraints:
The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability and
factors affecting the loop equation.
The value of F
frequencies below 100 MHz, F
To avoid crosstalk between the VCOs, the VCO frequencies should not be within 0.5% of each other nor
should their harmonics be within 0.5% of the other’s fundamental frequency.
The graphics controller’s clock synthesizers will seek the new frequency as soon as it is loaded following a
write to the control register. Any change in the post-divisor will take affect immediately. The output may
glitch during this transition of post divide values. Therefore, the programmer may wish to hold the post-
divisor value constant across a range of frequencies. There is also the consideration of changing from a
low frequency VCO value with a post-divide 1 (e.g., 100 MHz) to a high frequency
Although the beginning and ending frequencies are close together, the intermediate frequencies may cause
the graphics controller to fail in some environments. In this example, there will be a short-lived time during
which the output frequency will be approximately 25 MHz. The graphics controller provides the mux for
MCLK so it can select the fixed frequency (25.175 MHz) before programming a new frequency. Because
of this, the bus interface may not function correctly if the MCLK frequency falls below a certain value.
Register and memory accesses synchronized to MCLK may be too slow and violate the bus timing causing
a watchdog timer error.
Programming Example
The following is an example of the calculations which are performed.
Derive the proper programming word for a 25.175 MHz output frequency using a 14.31818 MHz reference
frequency.
The result:
Several choices for M and N are available:
&+,36
69000 Databook
VCO
1 MHz
150 KHz
100 MHz
3
3
Since 25.175 MHz < 100 MHz, quadruple it to 100.70 MHz to get F
Set the post divide (PD) divide by 4.
Video Loop Divisor Selector (VLD) = 1
F
M/N = 7.0330
VCO
must remain between 100 MHz and 220 MHz inclusive. Therefore, for output
M
N
= 100.70 = (14.31818 x M/N)
257
257
F
REF
F
F
REF
VCO
VCO
83 MHz
/(N)
must be brought into range by using the post-VCO Divisor.
220 MHz
211
204
Subject to Change Without Notice
M
5 MHz
30
29
N
Clock Generation
100.70
100.72
F
VCO
+0.00021
-0.00005
Error
VCO
4 (e.g., 220 MHz).
Revision 1.3 8/31/98
in its valid range.