B69000 Asiliant Technologies, B69000 Datasheet - Page 188

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3
2
1
Note: The reset state of this pin is also readable via bit 1 of the Host Bus Configuration Register (XR08).
0
&+,36
Pin CFG3
Reserved.
No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret
the state of the corresponding pin during reset.
Pin CFG2
Reserved.
No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret
the state of the corresponding pin during reset.
Pin CFG1
0: Indicates that VGA I/O Address decoding is disabled on the PCI Bus, so access to the registers
via I/O read and write operations is disabled.
1: Indicates that VGA I/O Address decoding is enabled on the PCI Bus, so access to the registers
via I/O read and write operations is enabled.
Reserved
This bit always returns the value of 1 when read.
69000 Databook
Subject to Change Without Notice
Extension Registers
Revision 1.3 8/31/98
14-21