ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet
ATmega169P Automotive
Specifications of ATmega169P Automotive
Related parts for ATmega169P Automotive
ATmega169P Automotive Summary of contents
Page 1
Features • High Performance, Low Power AVR • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at ...
Page 2
... PE2 (USCK/SCL/PCINT4) PE4 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega169P Automotive 2 Pinout ATmega169P LCDCAP 1 (RXD/PCINT0) PE0 2 INDEX CORNER ...
Page 3
... AVR CPU UNIVERSAL USART SERIAL INTERFACE DATA REGISTER DATA DIR. PORTE REG. PORTE PORTE DRIVERS PE0 - PE7 7735B–AVR–12/07 ATmega169P Automotive PA0 - PA7 PORTA DRIVERS DATA REGISTER DATA DIR. DATA REGISTER PORTA REG. PORTA 8-BIT DATA BUS INTERNAL OSCILLATOR STACK ...
Page 4
... ATmega169P have been verified during regular product qualification as per AEC-Q100 grade 3. As indicated in the ordering information paragraph, the products are available in industrial tem- perature grades, but with equivalent automotive quality and reliability objectives. Different temperature identifiers have been defined as listed in ATmega169P Automotive 4 Table 2-1. 7735B–AVR–12/07 ...
Page 5
... Table 2-1. Temperature -40 to +85°C 7735B–AVR–12/07 ATmega169P Automotive Temperature Grade Identification for Automotive Products Temperature Identifier T Similar to Industrial Temperature Grade but with Automotive Quality Comments 5 ...
Page 6
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega169P as listed on ”Alternate Functions of Port D” on page ATmega169P Automotive 6 73. 74. 77. ...
Page 7
... AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 7735B–AVR–12/07 81. , even if the ADC is not used. If the ADC is used, it should be connected ATmega169P Automotive ”Alternate Functions of Port F” on Table 27-3 on page CC 7 ...
Page 8
... This is the analog reference pin for the A/D Converter. 2.3.15 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in ure 22-2 on page capacitance reduces ripple on V ATmega169P Automotive 8 234. This capacitor acts as a reservoir for LCD power (V but increases the time until V LCD Fig- ) ...
Page 9
... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 7735B–AVR–12/07 ATmega169P Automotive 9 ...
Page 10
... These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". ATmega169P Automotive 10 7735B–AVR–12/07 ...
Page 11
... The program memory is In-System Reprogrammable Flash memory. 7735B–AVR–12/07 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega169P Automotive Data Bus 8-bit Status and Control Interrupt General Purpose Registrers Watchdog Timer ALU Analog ...
Page 12
... The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. ATmega169P Automotive 12 7735B–AVR–12/07 ...
Page 13
... The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7735B–AVR–12/07 ATmega169P Automotive ...
Page 14
... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega169P Automotive 14 shows the structure of the 32 general purpose working registers in the CPU. ...
Page 15
... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 7735B–AVR–12/07 ATmega169P Automotive The X-, Y-, and Z-registers ...
Page 16
... Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 5-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 5-5. Register Operands Fetch ALU Operation Execute ATmega169P Automotive – – – SP7 SP6 ...
Page 17
... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the 7735B–AVR–12/07 ATmega169P Automotive for details. ”Interrupts” on page 56 ”Boot Loader Support – Read-While-Write Self-Programming” on page ” ...
Page 18
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega169P Automotive 18 ; store SREG value ; disable interrupts during timed sequence ...
Page 19
... Timing diagrams for instruction fetch and execution are presented in ing” on page Figure 6-1. 7735B–AVR–12/07 ”Boot Loader Support – Read-While-Write Self-Programming” on page contains a detailed description on Flash data serial 16. Program Memory Map Program Memory Application Flash Section Boot Flash Section ATmega169P Automotive ”Instruction Execution Tim- 0x0000 0x1FFF 19 ...
Page 20
... Figure 6-2. 6.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 21. ATmega169P Automotive 20 shows how the ATmega169P SRAM Memory is organized. Data Memory Map Data Memory 32 Registers 64 I/O Registers 160 Ext I/O Reg ...
Page 21
... Figure 6-3. 7735B–AVR–12/07 On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ATmega169P Automotive T2 T3 Address valid Next Instruction 21 ...
Page 22
... EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. ATmega169P Automotive 22 307, ”Programming via the JTAG Interface” on page is likely to rise or fall slowly on power-up/down ...
Page 23
... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 7735B–AVR–12/07 ATmega169P Automotive EEPROM Programming Time Number of Calibrated RC Oscillator Cycles ...
Page 24
... EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATmega169P Automotive 24 ; 7735B–AVR–12/07 ...
Page 25
... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; ATmega169P Automotive 25 ...
Page 26
... BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. ATmega169P Automotive 26 the EEPROM data can be corrupted because the supply voltage is ...
Page 27
... Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at 7735B–AVR–12/07 ATmega169P Automotive – ...
Page 28
... EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. ATmega169P Automotive 28 7735B–AVR–12/07 ...
Page 29
... GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 6.6.2 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 6.6.3 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value 7735B–AVR–12/07 ATmega169P Automotive MSB R/W R/W R/W R ...
Page 30
... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATmega169P Automotive 30 presents the principal clock systems in the AVR and their distribution. All Clock Distribution Asynchronous General I/O ...
Page 31
... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 332. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ATmega169P Automotive (1) CKSEL3:0 1111 - 1000 0111 - 0110 0011, 0001, 0101, 0100 ”Typical Charac- = 3.0V) Number of Cycles CC 4 ...
Page 32
... When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7-4 Table 7-4. Power Conditions BOD enabled Fast rising power Slowly rising power Note: ATmega169P Automotive 32 and ”Internal Oscillator Speed” on page 349 ”System Clock Prescaler” on page 37 327. ”Calibration Byte” on page Internal Calibrated RC Oscillator Operating Modes Frequency Range (MHz) 7 ...
Page 33
... Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 This option should not be used with crystals, only with ceramic resonators. ATmega169P Automotive Figure 7-2. Either a quartz crystal or a XTAL2 (TOSC2) XTAL1 (TOSC1) GND Table Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 34
... Table 7-7 on page 34 Table 7-7. Note: The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 6.5 pF. Crystals with recommended 6.5 pF load capacitance can be without external capacitors as shown in ATmega169P Automotive 34 Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1:0 Power-save ...
Page 35
... Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application ATmega169P Automotive XTAL2 (TOSC2) XTAL1 (TOSC1) = 5.0V) Recommended Usage CC Fast rising power or BOD enabled Slowly rising power ...
Page 36
... MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to 37 for details. ATmega169P Automotive 36 External Clock Drive Configuration NC EXTERNAL CLOCK ...
Page 37
... Timer/Counter” on page 150 38. This feature can be used to decrease the system clock frequency and power , clk , and clk are divided by a factor as shown in ADC CPU FLASH ATmega169P Automotive for details on the oscillator and ”CLKPR – Clock Prescale Regis- Table 7-13. for further 37 ...
Page 38
... The division factors are given in Table 7-13. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to ATmega169P Automotive ...
Page 39
... ATmega169P Automotive CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 39 ...
Page 40
... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATmega169P Automotive 40 presents the different clock systems in the ATmega169P, and their distri- ...
Page 41
... This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in 7735B–AVR–12/07 ATmega169P Automotive and clk , while allowing the other clocks to run. CPU ...
Page 42
... PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See sleep modes, the clock is already stopped. ATmega169P Automotive 42 ”PRR – Power Reduction Register” on page ”Supply Current of I/O modules” on page 336 45, pro- for examples ...
Page 43
... Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to 7735B–AVR–12/07 ATmega169P Automotive ”AC - Analog Comparator” on page 211 for details on the start-up time. ”Watchdog Timer” on page 51 for details on how to configure the Watchdog Timer. ” ...
Page 44
... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega169P Automotive 44 ) and the ADC clock (clk ...
Page 45
... Standby mode is only recommended for use with external crystals or resonators – – – ATmega169P Automotive – SM2 SM1 SM0 R R/W R/W R Table Sleep Mode Idle ADC Noise Reduction Power-down Power-save ...
Page 46
... Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. Note: ATmega169P Automotive 46 The Analog Comparator is disabled using the ACD-bit in the and Status Register” ...
Page 47
... JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section scan” on page 256 7735B–AVR–12/07 ATmega169P Automotive Table 27-3 on page 328 ). POT ) and the Brown-out Detector is enabled. ...
Page 48
... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 9-2. TIME-OUT INTERNAL ATmega169P Automotive 48 Reset Logic Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor ...
Page 49
... VCC Max. start voltage to ensure internal Power- on Reset signal VCC Min. start voltage to ensure internal Power- on Reset signal VCC Rise Rate to ensure Power-on Reset 1. Before rising, the supply has to be between V ”System and Reset Characteristics” on page External Reset During Operation CC ATmega169P Automotive V RST t TOUT Min Typ 1.1 1.4 (1) 0 ...
Page 50
... Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 51 Figure 9-6. ATmega169P Automotive 50 /2 and /2.When the BOD is enabled, and V HYST ...
Page 51
... The WDR – Watchdog Reset – instruction resets the Watchdog WDT Configuration as a Function of the Fuse Settings of WDTON Safety WDT Initial Level State 1 Disabled 2 Enabled ATmega169P Automotive 328. To save power, the Table 9-3 on page How to Disable the How to Change Time- WDT out Timed sequence Timed sequence Always enabled Timed sequence levels ...
Page 52
... WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega169P Automotive 52 Watchdog Timer ...
Page 53
... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret (1) /* Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See ”About Code Examples” on page ATmega169P Automotive 10. 53 ...
Page 54
... This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. Watchdog Timer” on page 52. ATmega169P Automotive – ...
Page 55
... Also see Figure 28-33 on page 349. ATmega169P Automotive Typical Time-out at Typical Time-out 3. 15.4 ms 30.8 ms 61.6 ms 0.12 s 0.25 s 0.49 s 1 5.0V CC 14.7 ms 29.3 ms 58.7 ms 0.12 s 0.23 s 0. ...
Page 56
... Notes: ATmega169P Automotive 56 Reset and Interrupt Vectors Program (2) Address Source (1) 0x0000 RESET 0x0002 INT0 0x0004 PCINT0 0x0006 PCINT1 0x0008 TIMER2 COMP 0x000A TIMER2 OVF 0x000C TIMER1 CAPT 0x000E TIMER1 COMPA ...
Page 57
... SPM_RDY jmp LCD_SOF RESET: ldi r16, high(RAMEND); Main program start out SPH,r16 ldi r16, low(RAMEND) ATmega169P Automotive (1) Interrupt Vectors Start Address 0x0002 Boot Reset Address + 0x0002 0x0002 Boot Reset Address + 0x0002 Table 25-6 on page 289. For the BOOTRST Fuse “1” Comments ...
Page 58
... MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code ; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C2C ATmega169P Automotive 58 out SPL,r16 sei <instr> xxx ... ... ... ...
Page 59
... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis- abled while executing from the Boot Loader section. Refer to the section Read-While-Write Self-Programming” on page 277 ATmega169P Automotive ; Set Stack Pointer to top of RAM ; Enable interrupts 60. ...
Page 60
... Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the description in Space” on page ATmega169P Automotive ...
Page 61
... An example of timing of a pin change interrupt is shown in Figure 11-1. Pin Change Interrupt 7735B–AVR–12/07 ”Clock Systems and their Distribution” on page pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATmega169P Automotive 30. Figure 11-1 on page 61 pcint_in_(0) 0 pcint_syn pcint_setflag x clk 30. Low PCIF 61 ...
Page 62
... The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an ATmega169P Automotive ...
Page 63
... Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 7735B–AVR–12/07 ATmega169P Automotive ...
Page 64
... Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega169P Automotive ...
Page 65
... Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 7735B–AVR–12/07 ATmega169P Automotive and Ground as indicated in CC for a complete list of parameters. Pxn ...
Page 66
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATmega169P Automotive 66 (1) Pxn ...
Page 67
... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega169P Automotive Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 shows a timing dia- and t respectively ...
Page 68
... Figure 12-4. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin ATmega169P Automotive 68 SYSTEM CLK XXX ...
Page 69
... Figure 12-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega169P Automotive /2. CC 71. 69 ...
Page 70
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. ATmega169P Automotive 70 or GND is not recommended, since this may cause excessive currents if the pin is CC ...
Page 71
... SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port Figure 12-5 on page 71 are not shown in the succeeding tables. The overriding ATmega169P Automotive Figure 12-2 can be overridden by PUD ...
Page 72
... DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega169P Automotive 72 Generic Description of Overriding Signals for Alternate Functions Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override signal ...
Page 73
... Overriding Signals for Alternate Functions in PA7..PA4 PA7/SEG3 PA6/SEG2 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG3 SEG2 ATmega169P Automotive PA5/SEG1 PA4/SEG0 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG1 SEG0 ...
Page 74
... Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source. ATmega169P Automotive 74 Overriding Signals for Alternate Functions in PA3..PA0 PA3/COM3 PA2/COM2 LCDEN • ...
Page 75
... PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source. • SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI is activated when this pin is driven 7735B–AVR–12/07 ATmega169P Automotive 75 ...
Page 76
... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega169P Automotive 76 and Table 12-8 relate the alternate functions of Port B to the overriding signals Figure 12-5 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7..PB4 PB7/OC2A/ PB6/OC1B/ ...
Page 77
... SEG8 (LCD Front Plane 8) PC3 SEG9 (LCD Front Plane 9) PC2 SEG10 (LCD Front Plane 10) PC1 SEG11 (LCD Front Plane 11) PC0 SEG12 (LCD Front Plane 12) ATmega169P Automotive PB1/SCK/ PB0/SS/ PCINT9 PCINT8 SPE • MSTR SPE • MSTR PORTB1 • PUD PORTB0 • PUD SPE • ...
Page 78
... Table 12-11. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega169P Automotive 78 and Table 12-11 relate the alternate functions of Port C to the overriding signals Figure 12-5 on page 71. PC7/SEG5 PC6/SEG6 LCDEN LCDEN 0 0 LCDEN ...
Page 79
... ICP1/SEG22 – Port D, Bit 0 ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for Timer/Counter1. SEG22, LCD front plane 22 7735B–AVR–12/07 ATmega169P Automotive Alternate Function SEG15 (LCD front plane 15) SEG16 (LCD front plane 16) ...
Page 80
... Table 12-14. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega169P Automotive 80 and Table 12-14 relates the alternate functions of Port D to the overriding signals Figure 12-5 on page 71. PD7/SEG15 PD6/SEG16 LCDEN • LCDEN • (LCDPM>1) (LCDPM> LCDEN • ...
Page 81
... USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4) AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3) XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input or Pin Change Interrupt2) TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1) RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0) ATmega169P Automotive Table 12-15. 81 ...
Page 82
... Table 12-16. Overriding Signals for Alternate Functions PE7:PE4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: ATmega169P Automotive 82 and Table 12-17 relates the alternate functions of Port E to the overriding signals Figure 12-5 on page 71. PE6/DO/ PE7/PCINT7 PCINT6 (1) CKOUT ...
Page 83
... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega169P Automotive PE1/TXD/ PCINT1 TXENn 0 TXENn 1 ...
Page 84
... ADC3 - ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3-0. Table 12-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega169P Automotive PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 1 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN ...
Page 85
... T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23) T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24) SEG4 (LCD Front Plane 4) SEG13 (LCD Front Plane 13) SEG14 (LCD Front Plane 14) 1. Port G, PG5 is input only. Pull-up is always on. See Table 26-3 on page 294 for RSTDISBL fuse. ATmega169P Automotive PF1/ADC1 PF0/ADC0 ...
Page 86
... Table 12-22. Overriding Signals for Alternate Functions in PG4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega169P Automotive 86 and Table 12-22 relates the alternate functions of Port G to the overriding signals Figure 12-5 on page 71. – – PG4/T0/SEG23 LCDEN • (LCDPM>5) 0 LCDEN • (LCDPM>5) 1 ...
Page 87
... LCDEN • LCDEN (LCDPM> – – LCDEN • LCDEN (LCDPM> INPUT – SEG24 SEG4 ATmega169P Automotive PG1/SEG13 PG0/SEG14 LCDEN • LCDEN • (LCDPM>0) (LCDPM> LCDEN • LCDEN • (LCDPM>0) (LCDPM> – – LCDEN • ...
Page 88
... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 12.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 12.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value ATmega169P Automotive JTD - - PUD R R for more details about this feature ...
Page 89
... Bit 0x09 (0x29) Read/Write Initial Value 12.4.14 PORTE – Port E Data Register Bit 0x0E (0x2E) Read/Write Initial Value 12.4.15 DDRE – Port E Data Direction Register Bit 0x0D (0x2D) Read/Write Initial Value 7735B–AVR–12/07 ATmega169P Automotive PORTC7 PORTC6 PORTC5 PORTC4 R/W R/W R/W R ...
Page 90
... PORTG – Port G Data Register Bit 0x14 (0x34) Read/Write Initial Value 12.4.21 DDRG – Port G Data Direction Register Bit 0x13 (0x33) Read/Write Initial Value 12.4.22 PING – Port G Input Pins Address Bit 0x12 (0x32) Read/Write Initial Value ATmega169P Automotive PINE7 PINE6 PINE5 PINE4 R/W R/W R/W R/W N/A N/A N/A ...
Page 91
... The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 7735B–AVR–12/07 ATmega169P Automotive Figure 13-1. For the actual placement of I/O pins, refer to 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are 102 ...
Page 92
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram ATmega169P Automotive 92 for details. The compare match event will also set the Compare Flag Table 13-1 are also used extensively throughout the document. ...
Page 93
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 96. (See ”Modes of Operation” on page shows a block diagram of the Output Compare unit. ATmega169P Automotive in the following. T0 96.). 93 ...
Page 94
... All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. ATmega169P Automotive 94 DATA BUS OCRnx ...
Page 95
... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. 7735B–AVR–12/07 ATmega169P Automotive COMnx1 Waveform COMnx0 ...
Page 96
... OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. ATmega169P Automotive 96 See ”8-bit Timer/Counter Register Description” on page 102. ...
Page 97
... This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. 7735B–AVR–12/07 ATmega169P Automotive Figure 1 2 ...
Page 98
... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f ATmega169P Automotive 98 Figure 13-6. The TCNT0 value is in the timing diagram shown as a his- ...
Page 99
... OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See The actual OC0A value will only be visible on the port pin if the data direction for the port pin is 7735B–AVR–12/07 ATmega169P Automotive Figure 13-7 ...
Page 100
... MAX value in all modes other than phase correct PWM mode. Figure 13-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk I/O TCNTn TOVn Figure 13-9 ATmega169P Automotive 100 f OCnxPCPWM Figure 13-7 Figure 13-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled ...
Page 101
... OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega169P Automotive /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 102
... These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. ATmega169P Automotive 102 7 6 ...
Page 103
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 99 for more details. ATmega169P Automotive (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...
Page 104
... OC0A pin. 13.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable ATmega169P Automotive 104 Clock Select Bit Description CS01 CS00 Description clock source (Timer/Counter stopped) ...
Page 105
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. 7735B–AVR–12/07 ATmega169P Automotive – ...
Page 106
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM1 bit in enable Timer/Counter1 module ATmega169P Automotive 106 ”Pinout ATmega169P” on page ”16-bit Timer/Counter Register Description” on page ”PRR – Power Reduction Register” on page 45 Figure 14-1 ...
Page 107
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Table 12-5 on page Timer/Counter1 pin placement and description. ATmega169P Automotive (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform Generation ...
Page 108
... FOC1A and FOC1B are added to TCCR1C. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega169P Automotive 108 115.. The compare match event will also set the Compare 211.) The Input Capture unit includes a digital filtering unit (Noise The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 109
... Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See ”About Code Examples” on page 10. ATmega169P Automotive 109 ...
Page 110
... Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega169P Automotive 110 (1) (1) 1. See ”About Code Examples” on page 10. 7735B–AVR–12/07 ...
Page 111
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See ”About Code Examples” on page 10. ”Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega169P Automotive 135. 111 ...
Page 112
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see ATmega169P Automotive 112 shows a block diagram of the counter and its surroundings. ...
Page 113
... ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 7735B–AVR–12/07 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega169P Automotive Figure 14-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 114
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be ATmega169P Automotive 114 109. ...
Page 115
... DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega169P Automotive 118.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 116
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega169P Automotive 116 109. ”Accessing 16-bit Registers” ...
Page 117
... Note that some COM1x1:0 bit settings are reserved for certain modes of operation. The COM1x1:0 bits have no effect on the Input Capture unit. 7735B–AVR–12/07 Waveform Generator I/O See ”16-bit Timer/Counter Register Description” on page 128. ATmega169P Automotive Figure 14 OCnx 0 D ...
Page 118
... The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. ATmega169P Automotive 118 Table 14-1 on page 128. For fast PWM mode refer to 117.) ” ...
Page 119
... OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega169P Automotive Figure 14-6. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA ...
Page 120
... Figure 14-7. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A ATmega169P Automotive 120 ( log TOP R = ...
Page 121
... OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of f similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com- pare unit is enabled in the fast PWM mode. 7735B–AVR–12/07 ATmega169P Automotive Table on page f clk_I/O f ...
Page 122
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter- rupt Flag will be set when a compare match occurs. Figure 14-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATmega169P Automotive 122 ( ) log TOP + 1 ...
Page 123
... TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1 the OC1A output will toggle with a 50% duty cycle. 7735B–AVR–12/07 ATmega169P Automotive Figure 14-8 f clk_I/O f ...
Page 124
... The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATmega169P Automotive 124 14-9). R ...
Page 125
... TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). 7735B–AVR–12/07 ATmega169P Automotive shows the output generated is, in contrast to the phase correct mode, symmetri- ...
Page 126
... TCNTn OCRnx OCFnx Figure 14-11 Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f TCNTn OCRnx Figure 14-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams ATmega169P Automotive 126 Figure 14-10 clk I/O clk Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ...
Page 127
... I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega169P Automotive TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value ...
Page 128
... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 14-1. COM1A1/COM1B1 Table 14-2 PWM mode. Table 14-2. COM1A1/COM1B1 Note: ATmega169P Automotive 128 COM1A1 COM1A0 COM1B1 R/W R/W ...
Page 129
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. ”Phase Correct PWM Mode” on page 122. Table 14-4. Modes of operation supported by the Timer/Counter ATmega169P Automotive Description Normal port operation, OC1A/OC1B disconnected. WGM13 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). ...
Page 130
... This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. ATmega169P Automotive 130 (1) ...
Page 131
... I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – R/W R ATmega169P Automotive – – – – Figure 0 – ...
Page 132
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega169P Automotive 132 7 6 ...
Page 133
... ICIE1 (See ”Interrupts” on page 56.) is executed when the ICF1 Flag, located in TIFR1, is set. (See ”Interrupts” on page (See ”Interrupts” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega169P Automotive ICR1[15:8] ICR1[7:0] R/W R/W R/W R ...
Page 134
... TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega169P Automotive 134 – ...
Page 135
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 shows a functional equivalent block diagram of the T1/T0 synchronization and /clk clk I/O Synchronization ATmega169P Automotive /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O ...
Page 136
... An external clock source can not be prescaled. Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk I/O PSR10 T0 T1 Note: ATmega169P Automotive 136 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O Clear Synchronization Synchronization ...
Page 137
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 7735B–AVR–12/07 ATmega169P Automotive TSM – ...
Page 138
... Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register ATmega169P Automotive 138 ”Pinout ATmega169P” on page ”8-bit Timer/Counter Register Description” on page TCCRnx ...
Page 139
... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 16-2 shows a block diagram of the counter and its surrounding environment. 7735B–AVR–12/07 ATmega169P Automotive ). T2 for details. The compare match event will also set the Compare Table 16-1 are also used extensively throughout the section. ...
Page 140
... WGM21:0 bits and Com- pare Output mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page Figure 16-3 ATmega169P Automotive 140 DATA BUS count clear ...
Page 141
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 7735B–AVR–12/07 ATmega169P Automotive DATA BUS OCRnx = (8-bit Comparator ) ...
Page 142
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. ATmega169P Automotive 142 Waveform D ...
Page 143
... Table 16-3 on page 154, and for phase correct PWM refer to (See ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page ATmega169P Automotive 154. For fast PWM mode, refer to Table 16-5 on page 154. 142.). Figure 16-5. The counter value (TCNT2) Table 16-4 148 ...
Page 144
... In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATmega169P Automotive 144 1 ...
Page 145
... OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 7735B–AVR–12/07 ATmega169P Automotive Figure 16-6. The TCNT2 value is in the timing diagram shown as a his- 1 ...
Page 146
... The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or ATmega169P Automotive 146 1 ...
Page 147
... Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 7735B–AVR–12/07 ATmega169P Automotive f clk_I ----------------- - ⋅ ...
Page 148
... MAX value in all modes other than phase correct PWM mode. Figure 16-8. Timer/Counter Timing Diagram, no Prescaling TCNTn Figure 16-9 Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (f Figure 16-10 ATmega169P Automotive 148 contains timing data for basic Timer/Counter operation. The figure shows the clk I/O clk ...
Page 149
... I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega169P Automotive OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP /8) clk_I/O OCRnx + 2 149 ...
Page 150
... The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up ATmega169P Automotive 150 Enable interrupts, if needed. 7735B–AVR–12/07 ...
Page 151
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 7735B–AVR–12/07 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega169P Automotive 151 ...
Page 152
... TOSC1, the EXCLK bit in ASSR must be set. For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre- dictable prescaler. ATmega169P Automotive 152 clk clk I/O T2S Clear ...
Page 153
... The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 16-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits ATmega169P Automotive ...
Page 154
... Note: Table 16-5 rect PWM mode. Table 16-5. COM2A1 Note: ATmega169P Automotive 154 Compare Output Mode, non-PWM Mode COM2A0 Description 0 Normal port operation, OC2A disconnected. 1 Toggle OC2A on compare match. 0 Clear OC2A on compare match. 1 Set OC2A on compare match. shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM ...
Page 155
... The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. 7735B–AVR–12/07 ATmega169P Automotive Clock Select Bit Description CS21 CS20 Description ...
Page 156
... Read/Write Initial Value • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead ATmega169P Automotive 156 – ...
Page 157
... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 137 7735B–AVR–12/07 ATmega169P Automotive TSM – ...
Page 158
... The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169P and peripheral devices or between several AVR devices. The PRSPI bit in enable SPI module. Figure 17-1. SPI Block Diagram Note: ATmega169P Automotive 158 ”PRR – Power Reduction Register” on page 45 (1) DIVIDER /2/4/8/16/32/64/128 1 ...
Page 159
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles. 7735B–AVR–12/07 ATmega169P Automotive Figure SHIFT ENABLE 17-2. The sys- ...
Page 160
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega169P Automotive 160 Table 17-1. For more details on automatic port overrides, refer to 71 ...
Page 161
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. ”About Code Examples” on page 10 ATmega169P Automotive 161 ...
Page 162
... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega169P Automotive 162 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( ”About Code Examples” on page 10. ...
Page 163
... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 7735B–AVR–12/07 ATmega169P Automotive 163 ...
Page 164
... CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 17-3. SPI Transfer Format with CPHA = 0 Figure 17-4. SPI Transfer Format with CPHA = 1 ATmega169P Automotive 164 Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 17-4, as done below: ...
Page 165
... Figure 17-3 and Figure 17-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega169P Automotive CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 17-4 for an example. The CPOL ...
Page 166
... When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega169P is also used for program memory and EEPROM down- loading or uploading. See ATmega169P Automotive 166 Relationship Between SCK and the Oscillator Frequency SPR1 ...
Page 167
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 7735B–AVR–12/07 ATmega169P Automotive ...
Page 168
... The PRUSART0 bit in enable USART0 module. A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. ATmega169P Automotive 168 ”PRR – Power Reduction Register” on page 45 must be written to zero to Figure 18-1 on page 169. CPU ...
Page 169
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Table 12-13 on page pin placement. ATmega169P Automotive Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL Receiver ...
Page 170
... UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 18-2 ATmega169P Automotive 170 shows a block diagram of the clock generation logic. Figure 18-1) if the Buffer Registers are 7735B– ...
Page 171
... Input from XCK pin (internal Signal). Used for synchronous slave Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculat- ATmega169P Automotive U2X / ...
Page 172
... CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Note that f add some margin to avoid possible loss of data due to frequency variations. ATmega169P Automotive 172 Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud ...
Page 173
... Figure 18-4 on page 174 brackets are optional. 7735B–AVR–12/07 UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 18-3 shows, when UCPOLn is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside ATmega169P Automotive Sample Sample 173 ...
Page 174
... The relation between the parity bit and data bits is as follows: P even odd used, the parity bit is located between the last data bit and first stop bit of a serial frame. ATmega169P Automotive 174 FRAME (IDLE ...
Page 175
... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. 7735B–AVR–12/07 ATmega169P Automotive 175 ...
Page 176
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATmega169P Automotive 176 (1) UBRRH0, r17 UBRRL0, r16 r16, (1< ...
Page 177
... UCSR0A,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data sts UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See ”About Code Examples” on page 10. ATmega169P Automotive 177 ...
Page 178
... Put data into buffer, sends the data */ UDR0 = data; } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. ATmega169P Automotive 178 (1)(2) UCSR0B,TXB80 UCSR0B,TXB80 UDR0,r16 (1)(2) ...
Page 179
... The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo- ing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. 7735B–AVR–12/07 ATmega169P Automotive 179 ...
Page 180
... Get and return received data from buffer */ return UDR0; } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value. ATmega169P Automotive 180 (1) r16, UDR0 ( ...
Page 181
... FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. 7735B–AVR–12/07 ATmega169P Automotive 181 ...
Page 182
... Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega169P Automotive 182 (1) r18, UCSR0A ...
Page 183
... Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see 7735B–AVR–12/07 ”Parity Bit Calculation” on page 174 ATmega169P Automotive and ”Parity Checker” on page 184. 183 ...
Page 184
... The following code example shows how to flush the receive buffer. Assembly Code Example USART_Flush: sbis UCSR0A, RXC0 ret in rjmp USART_Flush C Code Example void USART_Flush( void ) { unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; } Note: ATmega169P Automotive 184 (1) r16, UDR0 (1) 1. See ”About Code Examples” on page 10. 7735B–AVR–12/07 ...
Page 185
... The sample RxD IDLE Sample (U2X = Sample (U2X = ATmega169P Automotive START Figure 18-6 on page 186 shows the sampling of the ...
Page 186
... The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 18-2 on page frames to the start bit. ATmega169P Automotive 186 RxD 1 2 ...
Page 187
... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104,35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega169P Automotive ( ) ----------------------------------- ( )S fast for normal speed and for normal speed and M Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4 ...
Page 188
... MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. ATmega169P Automotive 188 7735B–AVR–12/07 ...
Page 189
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 7735B–AVR–12/07 ATmega169P Automotive 189 ...
Page 190
... Bit 5 – UDREn: USART Data Register Empty n The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). ATmega169P Automotive 190 7 6 ...
Page 191
... Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 7735B–AVR–12/07 ATmega169P Automotive ”Multi-processor Communication Mode” on page 7 6 ...
Page 192
... This bit selects between asynchronous and synchronous mode of operation. Table 18-4. • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The ATmega169P Automotive 192 – ...
Page 193
... UCPOLn Bit Settings Transmitted Data Changed (Output of TxD Pin) Rising XCK Edge Falling XCK Edge ATmega169P Automotive Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZ0n Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved ...
Page 194
... UBRRLn contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRLn will trigger an immediate update of the baud rate prescaler. ATmega169P Automotive 194 15 ...
Page 195
... Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% -3.5% 7 0.0% -7.0% 5 0.0% 8.5% 3 0.0% 8.5% 2 0.0% 8.5% 1 0.0% -18.6% 1 -25.0% 8.5% 0 0.0% – – – – – – 125 kbps 115.2 kbps ATmega169P Automotive Table ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRRn Error UBRRn Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7.0% 7 ...
Page 196
... Max. 230.4 kbps 460.8 kbps 1. UBRRn = 0, Error = 0.0% ATmega169P Automotive 196 f = 4.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3. ...
Page 197
... Mbps ATmega169P Automotive f = 14.7456 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 383 0.0% 767 0.0% 191 0.0% 383 0.0% 95 0.0% 191 0.0% 63 0.0% 127 0.0% 47 0.0% 95 0.0% 31 0.0% 63 0.0% 23 0.0% 47 0.0% 15 0.0% 31 0.0% 11 0. ...
Page 198
... Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. ATmega169P Automotive 198 (Continued 16.0000 MHz osc U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error 416 -0.1% 832 0.0% 207 0.2% 416 -0.1% 103 0.2% 207 0.2% 68 0.6% 138 -0.1% 51 0.2% 103 ...
Page 199
... ATmega169P” on page 2. CPU accessible I/O Registers, including I/O bits 207 USIDR 4-bit Counter 1 0 [1] USISR 2 USICR ATmega169P Automotive (Output only) DO (Input/Open Drain) DI/SDA TIM0 COMP 0 (Input/Open Drain) USCK/SCL 1 CLOCK HOLD Two-wire Clock Control Unit 199 ...
Page 200
... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. ATmega169P Automotive 200 Bit7 Bit6 ...