ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet - Page 27

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ATmega169P Automotive

Manufacturer Part Number
ATmega169P Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega169P Automotive

Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
6.4
6.4.1
6.4.2
6.4.3
7735B–AVR–12/07
EEPROM Register Description
EEARH and EEARL – EEPROM Address Register
EEDR – EEPROM Data Register
EECR – EEPROM Control Register
• Bits 15:9 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
Bit
0x1F (0x3F)
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
7
R
0
X
7
0
7
0
EEAR6
R/W
R/W
14
R
R
X
6
0
6
0
6
0
EEAR5
R/W
R/W
13
R
R
X
5
0
5
0
5
0
EEAR4
R/W
R/W
12
R
4
0
R
X
4
0
4
0
ATmega169P Automotive
EEAR3
EERIE
R/W
R/W
R/W
11
3
0
R
X
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
10
R
X
2
0
2
0
2
0
EEAR1
EEWE
R/W
R/W
R/W
R
X
9
1
0
1
0
1
X
EEAR0
EEAR8
EERE
LSB
R/W
R/W
R/W
R/W
X
X
8
0
0
0
0
0
EEARH
EEARL
EEDR
EECR
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