ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet - Page 246

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ATmega169P Automotive

Manufacturer Part Number
ATmega169P Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega169P Automotive

Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
246
ATmega169P Automotive
• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in
selection.
Table 22-5.
The frame frequency can be calculated by the following equation:
Where:
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation
is shown in
Table 22-6.
clk
4 MHz
4 MHz
32.768 kHz
32.768 kHz
LCDCD2
LCD
0
0
0
0
1
1
1
1
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see
Table 22-5 on page
Table
LCDCD1
LCD Clock Divide
Example of frame rate calculation
duty
1/4
1/3
Static
1/2
0
0
1
1
0
0
1
1
22-6.
K
LCDCD0
8
6
8
8
0
1
0
1
0
1
0
1
Table
246. This Clock Divider gives extra flexibility in frame rate
N
2048
2048
16
16
22-5).
Output from Prescaler
f
frame
LCDCD2:0
divided by (D):
000
100
011
011
=
1
2
3
4
5
6
7
8
------------------------- -
(
K N D
f
clk
LCD
D
)
4
4
1
5
Duty = 1/4, gives a frame rate of:
clk
Frame Rate
4000000/(8*2048*4) = 61 Hz
4000000/(6*2048*4) = 81 Hz
32768/(8*16*1) = 256 Hz
32768/(8*16*5) = 51 Hz
LCD
= 32.768 kHz, N = 16, and
85.3 Hz
51.2 Hz
42.7 Hz
36.6 Hz
256 Hz
128 Hz
64 Hz
32 Hz
7735B–AVR–12/07

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