ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet - Page 234

• Manufacturer Part Number: ATmega169P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega169P Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.2.5
22.2.6
22.2.7
234
ATmega169P Automotive
LCD Contrast Controller/Power Supply
LCDCAP
LCD Buffer Driver
To energize a segment, an absolute voltage above a certain threshold must be applied. This is
done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase.
For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-
els must be applied. Otherwise, non-energized segments on COM0 would be energized for all
non-selected common.
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0
compared to none addressed COM lines. Non-energized segments are in phase with the
addressed COM0, and energized segments have opposite phase and large amplitude. For
waveform figures refer to
LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and
sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is
addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-
ous until all COM lines are addressed according to number of common (duty). The display data
are latched before a new frame start.
The peak value (V
by software from 2.6V to 3.35V independent of V
until V
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in
ure
ripple on V
It is possible to use an external power supply. This power can be applied to LCDCAP before
V
Figure 22-2. LCDCAP Connection
Intermediate voltage levels are generated from buffers/drivers. The buffers are active the
amount of time specified by LCDDC[2:0] in
247. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive time
will reduce power consumption, but displays with high internal resistance or capacitance may
need longer drive time to achieve sufficient contrast.
CC
. Externally applied V
22-2. This capacitor acts as a reservoir for LCD power (V
LCD
has reached its target value.
LCD
but increases the time until V
LCD
) on the output waveform determines the LCD Contrast. V
LCD
”Mode of Operation” on page
can be both above and below V
(Optional)
LCDCAP
V
62
63
64
LCD
”LCDCCR – LCD Contrast Control Register” on page
LCD
1
reaches its target value.
CC
. An internal signal inhibits output to the LCD
2
3
235. Latched data from LCDDR4 -
CC
LCD
. Maximum V
). A large capacitance reduces
LCD
LCD
is 5.5V
7735B–AVR–12/07
is controlled
Fig-