ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet - Page 245

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ATmega169P Automotive

Manufacturer Part Number
ATmega169P Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega169P Automotive

Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
22.5.3
7735B–AVR–12/07
LCDFRR – LCD Frame Rate Register
Table 22-3.
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in
22-4 on page
ing the LCD module.
Table 22-4.
Bit
(0xE6)
Read/Write
Initial Value
LCDPS2
LCDPM2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
245. Together they determine the prescaled LCD clock (clk
LCDPS1
LCD Port Mask
LCD Prescaler Select
LCDPM1
R
7
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LCDPS2
R/W
6
0
LCDPS0
0
1
0
1
0
1
0
1
LCDPM0
LCDPS1
0
1
0
1
0
1
0
1
R/W
5
0
Output from
clk
clk
clk
Prescaler
clk
clk
clk
clk
clk
clk
LCDPS0
LCD
LCD
LCD
LCD
LCD
LCD
I/O Port in Use as Segment
R/W
LCD
LCD
LCD
4
0
/1024
/2048
/4096
/128
/256
/512
/16
/64
ATmega169P Automotive
/N
SEG0:12
SEG0:14
SEG0:16
SEG0:18
SEG0:20
SEG0:22
SEG0:23
SEG0:24
Driver
R
3
0
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
LCDCD2
R/W
2
0
Frame Rate = 64 Hz
LCDCD1
R/W
130 kHz
260 kHz
520 kHz
8.1 kHz
1
0
33 kHz
66 kHz
1 MHz
2 MHz
Maximum Number of
LCD_PS
LCDCD0
Segments
), which is clock-
R/W
0
0
13
15
17
19
21
23
24
25
LCDFRR
Table
245

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