ATmega169P Automotive Atmel Corporation, ATmega169P Automotive Datasheet - Page 170

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ATmega169P Automotive

Manufacturer Part Number
ATmega169P Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega169P Automotive

Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
18.2.1
18.3
170
Clock Generation
ATmega169P Automotive
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
• Transmitter Operation.
• Transmit Buffer Functionality.
• Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
• A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
The following control bits have changed name, but have same functionality and register location:
• CHR9 is changed to UCSZn2.
• OR is changed to DORn.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCK pin is only active when using synchronous mode.
Figure 18-2
buffer. Therefore the UDRn must only be read once for each incoming data! More important is
the fact that the Error Flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered with
the data in the receive buffer. Therefore the status bits must always be read before the UDRn
Register is read. Otherwise the error status will be lost since the buffer state is lost.
received data to remain in the serial Shift Register (see
full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun
(DORn) error conditions.
shows a block diagram of the clock generation logic.
Figure
18-1) if the Buffer Registers are
7735B–AVR–12/07

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