ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 109

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

TIMSK –
Timer/Counter
Interrupt Mask
Register
TIFR – Timer/Counter
Interrupt Flag Register
2490Q–AVR–06/10
•
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFR.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the
data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
Bit
0x37 (0x57)
Read/Write
Initial Value
Bit
0x36 (0x56)
Read/Write
Initial Value
1. Write any value to either of the registers OCR0 or TCCR0.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT0.
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the interrupt flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
OCF2
R/W
7
0
OCIE2
R/W
7
0
TOV2
R/W
6
0
TOIE2
R/W
6
0
ICF1
R/W
TICIE1
5
0
R/W
5
0
OCF1A
R/W
OCIE1A
4
0
R/W
4
0
OCF1B
OCIE1B
R/W
R/W
3
0
3
0
TOV1
R/W
TOIE1
R/W
2
0
2
0
OCF0
OCIE0
R/W
R/W
1
0
1
0
ATmega64(L)
TOV0
TOIE0
R/W
R/W
0
0
0
0
TIMSK
TIFR
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