ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 330

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

SPI Timing
Characteristics
2490Q–AVR–06/10
See
Table 134. SPI Timing Parameters
Note:
Figure 157. SPI Interface Timing Requirements (Master Mode)
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 157 on page 330
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
Description
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
SCK to out high
SCK to SS high
- 2 t
- 3 t
SCK high/low
MISO
MOSI
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SCK
SCK
SS low to out
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
SS
CLCL
CLCL
Setup
Setup
Hold
Hold
for f
for f
CK
CK
(1)
<12 MHz
>12 MHz
6
4
MSB
and
5
MSB
Master
Master
Master
Master
Master
Master
Master
Master
Figure 158 on page 331
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
7
4 • t
2 • t
Min
10
20
20
t
ck
...
ck
ck
...
50% duty cycle
See
for details.
0.5 • t
Table 72
Typ
3.6
10
10
10
10
15
15
10
2
sck
LSB
1
ATmega64(L)
LSB
2
Max
1.6
3
8
ns
µs
ns
330