ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 44

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ATmega64

Manufacturer Part Number
ATmega64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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External Clock
2490Q–AVR–06/10
non-zero values to this register will increase the frequency of the internal Oscillator. Writing
0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to
time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than
10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that
the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz. Tuning to
other values is not guaranteed, as indicated in
Table 15. Internal RC Oscillator Frequency Range
To drive the device from an external clock source, XTAL1 should be driven as shown in
21. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between
XTAL1 and GND.
Figure 21. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 16. Start-up Times for the External Clock Selection
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
SUT1..0
OSCCAL Value
00
01
10
11
0xFF
16.
0x00
0x7F
Start-up Time from Power-
down and Power-save
Min Frequency in Percentage of
6 CK
6 CK
6 CK
Nominal Frequency (%)
100
EXTERNAL
50
75
SIGNAL
CLOCK
Additional Delay from
Reset (V
Reserved
Table
4.1 ms
65 ms
CC
15.
= 5.0 V)
Max Frequency in Percentage of
Nominal Frequency (%)
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
100
150
200
ATmega64(L)
Figure
44

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