ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 39

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

XDIV – XTAL Divide
Control Register
Default Clock
Source
Crystal Oscillator
2490Q–AVR–06/10
The XTAL Divide Control Register is used to divide the source clock frequency by a number in
the range 2 - 129. This feature can be used to decrease power consumption when the require-
ment for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk
clk
can be written run-time to vary the clock frequency as suitable to the application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of
these bits is denoted d, the following formula defines the resulting CPU and peripherals clock
frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to
one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When
XDIVEN is written to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As
the divider divides the master clock input to the MCU, the speed of all peripherals is reduced
when a division factor is used.
Note:
The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is
therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all
users can make their desired clock source setting using an In-System or Parallel Programmer.
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-
figured for use as an On-chip Oscillator, as shown in
ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator
amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to-
rail swing on the output. This mode is suitable when operating in a very noisy environment or
when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency
range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces
power consumption considerably. This mode has a limited frequency range and it cannot be
used to drive other clock buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with
CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The
optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray
capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in
capacitor values given by the manufacturer should be used.
Bit
0x3C (0x5C)
Read/Write
Initial Value
ADC
, clk
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The
frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down
Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may
fail.
CPU
clk
:
, clk
XDIVEN
R/W
7
0
FLASH
) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit
XDIV6
R/W
6
0
XDIV5
R/W
5
0
f
CLK
XDIV4
R/W
4
0
=
Source clock
--------------------------------- -
XDIV3
129 d
R/W
3
0
–
XDIV2
Figure
R/W
Table
2
0
19. Either a quartz crystal or a
8. For ceramic resonators, the
XDIV1
R/W
1
0
ATmega64(L)
XDIV0
R/W
0
0
XDIV
I/O
39
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