ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 257

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

IDCODE; 0x1
SAMPLE_PRELOAD;
0x2
AVR_RESET; 0xC
BYPASS; 0xF
2490Q–AVR–06/10
•
Optional JTAG instruction selecting the 32-bit ID-Register as data register. The ID-Register con-
sists of a version number, a device number and the manufacturer code chosen by JEDEC. This
is the default instruction after Power-up.
The active states are:
•
•
Mandatory JTAG instruction for taking a snap-shot of the input/output pins without affecting the
system operation, and pre-loading the output latches. However, the output latches are not con-
nected to the pins. The Boundary-scan Chain is selected as data register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as data register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
Update-DR: Data from the scan chain is applied to output pins.
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However,
the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
ATmega64(L)
257