ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 128

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2490Q–AVR–06/10
Figure 53. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the compare registers. If the TOP value is lower than any of the com-
pare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note
that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx
Registers are written. As the third period shown in
actively while the Timer/Counter is running in the phase correct mode can result in an unsym-
metrical output. The reason for this can be found in the time of update of the OCRnx Register.
Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies
that the length of the falling slope is determined by the previous TOP value, while the length of
the rising slope is determined by the new TOP value. When these two values differ the two
slopes of the period will differ in length. The difference in length gives the unsymmetrical result
on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx1:0 to three (See
The actual OCnx value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx
Register at the Compare Match between OCRnx and TCNTn when the counter increments, and
clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
TCNTn
OCnx
OCnx
Period
1
f
OCnxPCPWM
2
=
--------------------------- -
2 N TOP
⋅
f
Figure 53
clk_I/O
3
⋅
illustrates, changing the TOP
ATmega64(L)
4
Table 60 on page
OCRnx / TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
135).
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