ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 328

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Two-wire Serial Interface Characteristics
Table 133
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to
Table 133. Two-wire Serial Bus Requirements
Notes:
2490Q–AVR–06/10
Symbol
V
V
V
V
t
t
t
I
C
f
Rp
t
t
t
t
t
t
t
t
r
of
SP
i
SCL
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
(1)
IL
IH
hys
OL
i
(1)
(1)
(1)
(1)
(1)
1. In ATmega64, this parameter is characterized and not 100% tested.
2. Required only for f
3. C
4. f
describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64 Two-wire Serial
Parameter
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both SDA and SCL
Output Fall Time from V
Spikes Suppressed by Input Filter
Input Current each I/O Pin
Capacitance for each I/O Pin
SCL Clock Frequency
Value of Pull-up resistor
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
Figure
SCL
156.
> 100 kHz.
IHmin
to V
ILmax
f
CK
(4)
10 pF < C
0.1 V
> max(16f
3 mA sink current
f
SCL
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
CC
Condition
≤ 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
< V
b
SCL
< 400 pF
i
< 0.9 V
, 250 kHz)
(5)
CC
(3)
(5)
20 + 0.1C
20 + 0.1C
V
----------------------------
V
----------------------------
0.05 V
CC
CC
0.7 V
3 mA
3 mA
Min
-0.5
250
100
-10
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
4.7
–
–
0
–
0
0
0
0
0.4V
0.4V
CC
CC
b
b
(2)
(3)(2)
(3)(2)
ATmega64(L)
V
1000 ns
-------------------- -
0.3 V
CC
300 ns
----------------- -
Max
50
3.45
300
250
400
0.4
0.9
C
10
10
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ 0.5
b
(2)
b
CC
Units
kHz
µA
pF
ns
µs
ns
µs
Ω
V
328