ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 28

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

ATmega103
Compatibility
Using the External
Memory Interface
Address Latch
Requirements
2490Q–AVR–06/10
Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended I/O
space. In ATmega103 compatibility mode, these registers are not available, and the features
selected by these registers are not available. The device is still ATmega103 compatible, as
these features did not exist in ATmega103. The limitations in ATmega103 compatibility mode
are:
•
•
•
•
•
The interface consists of:
•
•
•
•
•
The control bits for the External Memory Interface are located in three registers, the MCU Con-
trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External
Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the Data
Direction Registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 13
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address-, data- and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the external memory interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
latch (typically 74 × 573 or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
external memory interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
•
•
•
The external memory interface is designed to guaranty minimum address hold time after G is
asserted low of t
D to Q propagation delay (t
requirement of the external component. The data setup time before G low (t
address valid to ALE low (t
Only two wait-state settings are available (SRW1n = 0b00 and SRW1n = 0b01).
The number of bits that are assigned to address high byte are fixed.
The external memory section cannot be divided into sectors with different wait-state
settings.
Bus Keeper is not available.
RD, WR, and ALE pins are output only (Port G in ATmega64).
AD7:0: Multiplexed low-order address bus and data bus.
A15:8: High-order address bus (configurable number of bits).
ALE: Address latch enable.
RD: Read strobe.
WR: Write strobe.
D to Q propagation delay (t
Data setup time before G low (t
Data (address) hold time after G low (
(this figure shows the wave forms without wait states). When ALE goes from high-to-low,
Figure 12
h
= 5 ns (refer to t
illustrates how to connect an external SRAM to the AVR using an octal
AVLLC
pd
) must be taken into consideration when calculating the access time
pd
) minus PCB wiring delay (dependent on the capacitive load).
).
LAXX_LD
su
).
/t
th
LLAXX_ST
).
in
Table 137
“I/O Ports” on page
to
Table 144 on page
ATmega64(L)
su
) must not exceed
66. The XMEM
337). The
Fig-
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