ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 158

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2490Q–AVR–06/10
Table 64. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
Normal or CTC mode (non-PWM).
Table 65. Compare Output Mode, non-PWM Mode
Table 66
mode.
Table 66. Compare Output Mode, Fast PWM Mode
Note:
Table 67
PWM mode.
Mode
0
1
2
3
COM21
COM21
0
0
1
1
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
WGM21
shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM
(CTC2)
Table 65
However, the functionality and location of these bits are compatible with previous versions of
the timer.
Match is ignored, but the set or clear is done at BOTTOM. See
for more details.
0
0
1
1
COM20
COM20
WGM20
(PWM2)
0
1
0
1
0
1
0
1
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on Compare Match.
Clear OC2 on Compare Match.
Set OC2 on Compare Match.
Description
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode).
Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode).
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
(1)
TOP
0xFF
0xFF
OCR2
0xFF
(1)
Update of
OCR2
TOP
Immediate
Immediate
BOTTOM
“Fast PWM Mode” on page 152
ATmega64(L)
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
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