ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 135

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2490Q–AVR–06/10
Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
COMnA1/
COMnB1/
COMnC1
0
0
1
1
1. A
COMnA1/COMnB1/COMnC1 is set.
details.
special
COMnA0/
COMnB0/
COMnC0
0
1
0
1
case
Description
Normal port operation, OCnA/OCnB/OCnC disconnected.
WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match,
OCnB/OCnC disconnected (normal port operation).
Forr all other WGMn settings, normal port operation,
OCnA/OCnB/OCnC disconnected.
Clear OCnA/OCnB/OCnC on Compare Match when up-
counting. Set OCnA/OCnB/OCnC on Compare Match when
downcounting.
Set OCnA/OCnB/OCnC on Compare Match when up-counting.
Clear OCnA/OCnB/OCnC on Compare Match when
downcounting.
occurs
Table
61. Modes of operation supported by the Timer/Counter
when
(See “Modes of Operation” on page
See “Phase Correct PWM Mode” on page 127.
OCRnA/OCRnB/OC
Rn
ATmega64(L)
C
equals
124.)
TOP
for more
(1)
135
and