ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 248

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5.3.2
14.5.3.3
14.5.4
32142A–12/2011
Digital Frequency Locked Loop (DFLL) Operation
Disabling the PLL
PLL Lock
Factor (PLLDIV) fields must be written with the multiplication and division factors, respectively.
The PLLMUL must always be greater than 1, creating the PLL frequency:
The PLL Options (PLLOPT) field should be configured to proper values according to the PLL
operating frequency. The PLLOPT field can also be configured to divide the output frequency of
the PLL by 2 and Wide-Bandwidth mode, which allows faster startup time and out-of-lock time.
It is not possible to change any of the PLL configuration bits when the PLL is enabled, Any write
to PLLn while the PLL is enabled will be discarded.
After setting up the PLL, the PLL is enabled by writing a one to the PLL Enable (PLLEN) bit in
the PLLn register.
The PLL is disabled by writing a zero to the PLL Enable (PLLEN) bit in the PLLn register. After
disabling the PLL, the PLL configuration fields becomes writable.
The lock signal for each PLL is available as a PLLLOCKn flag in the PCLKSR register. If the lock
for some reason is lost, the PLLLOCKLOSTn flag in PCLKSR register will be set. An interrupt
can be generated on a 0 to 1 transition of these bits.
Rev: 2.1.0.1
The DFLL is controlled by the Digital Frequency Locked Loop Interface (DFLLIF). The DFLL is
disabled by default, but can be enabled to provide a high-frequency source clock for synchro-
nous and generic clocks.
Features:
The DFLL can operate in both open loop mode and closed loop mode. In closed loop mode a
low frequency clock with high accuracy can be used as reference clock to get high accuracy on
the output clock (CLK_DFLL).
To prevent unexpected writes due to software bugs, write access to the configuration registers is
protected by a locking mechanism. For details please refer to the UNLOCK register description.
• Internal oscillator with no external components
• 20-150MHz frequency in closed loop mode
• Can operate standalone as a high-frequency programmable oscillator in open loop mode
• Can operate as an accurate frequency multiplier against a known frequency in closed loop
• Optional spread-spectrum clock generation
• Very high-frequency multiplication supported - can generate all frequencies from a 32KHz
mode
clock
f
f
vco
vco
= (PLLMUL+1)/PLLDIV • f
= 2•(PLLMUL+1) • f
REF
, if PLLDIV = 0
REF
, if PLLDIV >0
ATUC64/128/256L3/4U
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