ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 453
ATUC64L4U
Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC64L4U
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATUC64L4U-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATUC64L4U-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATUC64L4U-U
Manufacturer:
ATMEL
Quantity:
20
Part Number:
ATUC64L4U-ZUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 453 of 960
- Download datasheet (15Mb)
20.6.5.9
20.6.5.10
Figure 20-25. Response Data Length
32142A–12/2011
Break
Sync
Node Action
LIN Response Data Length
Sync
Field
After an identifier transaction, a LIN response mode has to be selected. This is done in the Node
Action field (LINMR.NACT). Below are some response modes exemplified in a small LIN cluster:
The response data length is the number of data fields (bytes), excluding the checksum.
The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (IDCHR), in accordance to LIN 1.1. The user selects mode by writing to the Data
Length Mode bit (LINMR.DML):
• PARDIS=0: During header transmission, the parity bits are computed and in the shift register
• PARDIS=1: During header transmission, all the bits in IDCHR are sent on the bus. During
• Response, from master to slave1:
• Response, from slave1 to master:
• Response, from slave1 to slave2:
• DLM=0: the response data length is configured by the user by writing to the 8-bit Data Length
they replace bits six and seven from IDCHR. During header reception, the parity bits are
checked and can generate a LIN Identifier Parity Error (see
seven in IDCHR read as zero when receiving.
header reception, all the bits in IDCHR are updated with the received Identifier.
Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.
Master: NACT=PUBLISH
Slave1: NACT=SUBSCRIBE
Slave2: NACT=IGNORE
Master: NACT=SUBSCRIBE
Slave1: NACT=PUBLISH
Slave2: NACT=IGNORE
Master: NACT=IGNORE
Slave1: NACT=PUBLISH
Slave2: NACT=SUBSCRIBE
Identifier
Field
Data
Field
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Data
Field
Field
Data
ATUC64/128/256L3/4U
Section
20.6.6). Bits six and
Data
Field
Checksum
Field
453
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