ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 688

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.4
28.5
28.5.1
28.5.2
28.5.3
28.5.4
32142A–12/2011
I/O Lines Description
Product Dependencies
I/O lines
Clocks
DMA
Interrupts
Table 28-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed
with I/O Controller lines.
Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.
The clock for the ABDACB bus interface (CLK_ABDACB) is generated by the Power Manager.
This clock is turned on by default, and can be enabled and disabled in the Power Manager. It is
recommended to disable the ABDACB before disabling the clock, to avoid freezing the ABDACB
in an undefined state. Before using the Audio Bitstream DAC, the user must ensure that the
Audio Bitstream DAC clock is enabled in the Power Manager.
The Audio Bitstream DAC requires a separate clock for the D/A conversion. This clock is pro-
vided by a generic clock which has to be set up in the System Control Interface (SCIF). The
frequency for this clock has to be set as described in
this clock is accurate and has low jitter. Incorrect frequency will result in too fast or too slow play-
back (frequency shift), and too high jitter will add noise to the D/A conversion. For best
performance one should trade frequency accuracy (within some limits) for low jitter to obtain the
best performance as jitter will have large impact on the quality of the converted signal.
The ABDACB is connected to the Peripheral DMA controller. Using DMA to transfer data sam-
ples requires the Peripheral DMA controller to be programmed before enabling the ABDACB.
The ABDACB interrupt request line is connected to the interrupt controller. Using the ABDACB
interrupt requires the interrupt controller to be programmed first.
Pin Name
DAC[0]
DACN[0]
DAC[1]
DACN[1]
CLK
I/O Lines Description
Pin Description
Output for channel 0
Inverted output for channel 0
Output for channel 1
Inverted output for channel 1
Clock output for DAC
Table 28-3 on page
ATUC64/128/256L3/4U
697. It is important that
Type
Output
Output
Output
Output
Output
688