ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 714

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.5.4
29.5.5
29.5.6
29.5.7
29.6
29.6.1
29.6.2
32142A–12/2011
Functional Description
DMA
Interrupts
Peripheral Events
Debug Operation
Initializing the ADCIFB
Basic Operation
The ADCIFB DMA handshake interface is connected to the Peripheral DMA Controller. Using
the ADCIFB DMA functionality requires the Peripheral DMA Controller to be programmed first.
The ADCIFB interrupt request line is connected to the interrupt controller. Using the ADCIFB
interrupt request functionality requires the interrupt controller to be programmed first.
The ADCIFB peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details
When an external debugger forces the CPU into debug mode, this module continues normal
operation. If this module is configured in a way that requires it to be periodically serviced by the
CPU through interrupt requests or similar, improper operation or data loss may result during
debugging.
The ADCIFB embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter
(ADC). The ADC supports 8-bit or 10-bit resolution, which can be extended to 11 or 12 bits by
the Enhanced Resolution Mode.
The conversion is performed on a full range between 0 V and the reference voltage pin
ADVREFP. Analog inputs between these voltages converts to digital values (codes) based on a
linear conversion. This linear conversion is described in the expression below where M is the
number of bits used to represent the analog value, Vin is the voltage of the analog value to con-
vert, Vref is the maximum voltage, and Code is the converted digital value.
The ADC Interface is enabled by writing a one to the Enable bit in the Control Register (CR.EN).
After the ADC Interface is enabled, the ADC timings needs to be configured by writing the cor-
rect values to the RES, PRESCAL, and STARTUP fields in the ADC Configuration Register
(ACR). See
I/O Controller must be configured correctly and the Reference Voltage (ADVREFP) signal must
be connected. Refer to
To convert analog values to digital values the user must first initialize the ADCIFB as described
in
writing a one the corresponding bits in the Channel Enable Register (CHER). Enabling channel
N instructs the ADCIFB to convert the analog voltage applied to AD pin N at each conversion
sequence. Multiple channels can be enabled resulting in multiple AD pins being converted at
each conversion sequence.
Section
29.6.1. When the ADCIFB is initialized the channels to convert must be enabled by
Section
29.6.5, and
Section 29.5.1
Section 29.6.7
for details.
Code
=
for details. Before the ADCIFB can be used, the
2
------------------- -
M
V
ref
V
ATUC64/128/256L3/4U
in
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