ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 88

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.6.2
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.2.5
8.6.2.6
32142A–12/2011
USBC Device Mode Operation
Device Enabling
Endpoint activation
Data toggle sequence
Busy bank enable
Address setup
USB reset
In device mode, the USBC supports full- and low-speed data transfers.
Including the default control endpoint, a total of seven endpoints are provided. They can be con-
figured as isochronous, bulk or interrupt types, as described in
After a hardware reset, the USBC device mode is in the reset state (see
state, the endpoint banks are disabled and neither DP nor DM are pulled up (DETACH is one).
DP or DM will be pulled up according to the selected speed as soon as the DETACH bit is writ-
ten to zero. See
When the USBC is enabled (USBE is one) in device mode, it enters the Idle state, minimizing
power consumption. Being in Idle state does not require the USB clocks to be activated.
The USBC device mode can be disabled or reset at any time by disabling the USBC (by writing
a zero to USBE).
The USB bus reset is initiated by a connected host and managed by hardware.
When a USB reset state is detected on the USB bus, the following operations are performed by
the controller:
When an endpoint is disabled (UERST.EPENn = 0) the data toggle sequence, Endpoint n Status
Set (UESTAn), and UECONn registers will be reset. The controller ignores all transactions to
this endpoint as long as it is inactive.
To complete an endpoint activation, the user should fill out the endpoint descriptor: see
5 on page
In order to respond to a CLEAR_FEATURE USB request without disabling the endpoint, the
user can clear the data toggle sequence by writing a one to the Reset Data Toggle Set bit in the
Endpoint n Control Set register (UECONnSET.RSTDTS)
In order to make an endpoint bank look busy regardless of its actual state, the user can write a
one to the Busy Bank Enable bit in the Endpoint n Control Register (UECONnSET.BUSY0/1ES).
If a BUSYnE bit is set, any transaction to this bank will be rejected with a NAK reply.
The USB device address is set up according to the USB protocol.
• UDCON register is reset except for the DETACH and SPDCONF bits.
• Device Frame Number Register (UDFNUM), Endpoint n Configuration Register (UECFGn),
• The data toggle sequencing in all the endpoints are cleared.
• At the end of the reset process, the End of Reset (EORST) bit in the UDINT register is set.
and Endpoint n Control Register (UECONn) registers are cleared.
91.
“Device mode”
for further details.
ATUC64/128/256L3/4U
Table 8-1 on page 81
Section
8.6.1.1). In this
Figure 8-
88