ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 35

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. Memories
5.1
5.2
Table 5-1.
Table 5-2.
32142A–12/2011
Memory
Embedded SRAM
Embedded Flash
SAU Channels
HSB-PB Bridge B
HSB-PB Bridge A
ATUC256L3U,
ATUC128L3U,
ATUC256L4U
ATUC128L4U
ATUC64L3U,
ATUC64L4U
Embedded Memories
Physical Memory Map
Device
ATUC64/128/256L3/4U Physical Memory Map
Flash Memory Parameters
•
•
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even during boot. Note that AVR32 UC CPU uses unseg-
mented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address
space is mapped as follows:
Start Address
0x00000000
0x80000000
0x90000000
0xFFFE0000
0xFFFF0000
Internal high-speed flash
Internal high-speed SRAM, single-cycle access at full speed
Flash Size (FLASH_PW)
– 256Kbytes (ATUC256L3U, ATUC256L4U)
– 128Kbytes (ATUC128L3U, ATUC128L4U)
– 64Kbytes (ATUC64L3U, ATUC64L4U)
– 32Kbytes (ATUC256L3U, ATUC256L4U, ATUC128L3U, ATUC128L4U)
– 16Kbytes (ATUC64L3U, ATUC64L4U)
• 0 wait state access at up to 25MHz in worst case conditions
• 1 wait state access at up to 50MHz in worst case conditions
• Pipelined flash architecture, allowing burst reads from sequential flash locations, hiding
• Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, bootloader protection, security bit
• 32 fuses, erased during chip erase
• User page for data to be preserved during chip erase
256Kbytes
128Kbytes
64Kbytes
penalty of 1 wait state access
to only 8% compared to 0 wait state operation
Size
ATUC256L3U, ATUC256L4U
32Kbytes
256Kbytes
256 bytes
64Kbytes
64Kbytes
Number of Pages (FLASH_P)
512
256
128
ATUC128L3U, ATUC128L4U
32Kbytes
128Kbytes
256 bytes
64Kbytes
64Kbytes
ATUC64/128/256L3/4U
Page Size (FLASH_W)
ATUC64L3U, ATUC64L4U
16Kbytes
64Kbytes
256 bytes
64Kbytes
64Kbytes
512 bytes
512 bytes
512 bytes
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