ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 687

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28. Audio Bit Stream DAC (ABDACB)
28.1
28.2
28.3
32142A–12/2011
Features
Overview
Block Diagram
Rev.: 1.0.0.0
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The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported making the
Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of comple-
mentary digital outputs, DAC and DACN, which can be connected to an external high input
impedance amplifier.
The Audio Bitstream DAC is made up of several signal processing blocks and a 3rd order Sigma
Delta D/A converter for each channel. The Sigma Delta modulator converts the parallel data to a
bitstream, while the signal processing blocks perform volume control, offset control, upsampling,
and filtering to compensate for the upsampling process. The upsampling is performed by a Cas-
caded Integrator-Comb (CIC) filter, and the compensation filter is a Finite Impulse Response
(FIR) CIC compensation filter.
Figure 28-1. ABDACB Block Diagram
16 bit digital stereo DAC
Oversampling D/A conversion architecture
Digital bitstream output
Parallel interface
Connects to DMA for background transfer without CPU intervention
Supported sampling frequencies
Supported data formats
Common mode offset control
Volume control
– Adjustable oversampling ratio
– 3rd order Sigma-Delta D/A converters
– 8000Hz, 11025Hz, 12000Hz, 16000Hz, 22050Hz, 24000Hz, 32000Hz, 44100Hz, and 48000Hz
– 32-, 24-, 20-, 18-, 16-, and 8-bit stereo format
– 16- and 8-bit compact stereo format, with left and right sample packed in the same word to
reduce data transfers
clk_abdacb
gclk
(before up-sam pling)
Signal processing
ATUC64/128/256L3/4U
Sigm a D elta
M odulator
Sigm a D elta
M odulator
divider
C lock
D AC[1]
CLK
D AC[0]
DAC N[0]
DAC N[1]
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