ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 864

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.5.1.1
32142A–12/2011
Notation
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
Other security mechanisms can also restrict these functions. If such mechanisms are present
they are listed in the SAB address map section.
Table 34-10 on page 864
ter corresponds to one bit, and eight bits are grouped together for readability. The least
significantbit is always shifted first, and the most significant bit shifted last. The symbols used
are shown in
Table 34-9.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern " aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is
34 bits, but the test or debug unit may choose to shift only 8 bits " aaaaaaar ".
The following describes how to interpret the fields in the instruction description tables:
Table 34-10. Instruction Description
Instruction
IR input value
IR output value
Symbol
0
1
a
b
d
e
p
s
x
r
Description
Constant low value - always reads as zero.
Constant high value - always reads as one.
An address bit - always scanned with the least significant bit first
A busy bit. Reads as one if the SAB was busy, or zero if it was not. See
details on how the busy reporting works.
A data bit - always scanned with the least significant bit first.
An error bit. Reads as one if an error occurred, or zero if not. See
details on how the error reporting works.
The chip protected bit. Some devices may be set in a protected state where access to chip
internals are severely restricted. See the documentation for the specific device for details.
On devices without this possibility, this bit always reads as zero.
A direction bit. Set to one to request a read, set to zero to request a write.
A size bit. The size encoding is described where used.
A don’t care bit. Any value can be shifted in, and output data should be ignored.
Table
Symbol Description
34-9.
Description
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
convenience.
Example: 10000 (0x10)
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
Example: peb01
shows bit patterns to be shifted in a format like " peb01 ". Each charac-
ATUC64/128/256L3/4U
Section 34.4.11.5
Section 34.4.11.4
for
for
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