ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 359
ATUC64L4U
Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC64L4U
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATUC64L4U-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATUC64L4U-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATUC64L4U-U
Manufacturer:
ATMEL
Quantity:
20
Part Number:
ATUC64L4U-ZUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 359 of 960
- Download datasheet (15Mb)
16.6.1
Name:
Access Type:
Offset:
Reset Value:
• KEY
• TBAN: Time Ban Prescale Select
• CSSEL: Clock Source Select
• CEN: Clock Enable
• PSEL: Time Out Prescale Select
• FCD: Flash Calibration Done
• SFV: WDT Control Register Store Final Value
• MODE: WDT Mode
32142A–12/2011
FCD
31
23
15
7
-
-
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads
as zero.
Counter bit TBAN is used as watchdog “banned” time frame. In this time frame clearing the WDT timer is forbidden, otherwise a
watchdog reset is generated and the WDT timer is cleared.
0: Select the system RC oscillator (RCSYS) as clock source.
1: Select the 32KHz crystal oscillator (OSC32K) as clock source.
0: The WDT clock is disabled.
1: The WDT clock is enabled.
Counter bit PSEL is used as watchdog timeout period.
This bit is set after any reset.
0: The flash calibration will be redone after a watchdog reset.
1: The flash calibration will not be redone after a watchdog reset.
0: WDT Control Register is not locked.
1: WDT Control Register is locked.
Once locked, the Control Register can not be re-written, only a reset unlocks the SFV bit.
0: The WDT is in basic mode, only PSEL time is used.
1: The WDT is in window mode. Total timeout period is now TBAN+PSEL.
Writing to this bit when the WDT is enabled has no effect.
Control Register
30
22
14
6
-
-
CTRL
Read/Write
0x000
0x00010080
29
21
13
5
-
-
TBAN
28
20
12
4
-
KEY
SFV
27
19
11
3
MODE
ATUC64/128/256L3/4U
PSEL
26
18
10
2
CSSEL
DAR
25
17
9
1
CEN
EN
24
16
8
0
359
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