ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 489

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.7.2
Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
32142A–12/2011
SPCK cycle (for reference)
Data Transfer
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
SPCK
SPCK
MOSI
MISO
NSS
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 21-2 on page 489
Table 21-2.
Figure 21-3 on page 489
MSB
1
MSB
*** Not Defined, but normaly MSB of previous character received
SPI modes
2
6
6
SPI Mode
0
1
2
3
3
shows the four modes and corresponding parameter settings.
and
5
5
Figure 21-4 on page 490
4
4
4
5
3
3
6
2
2
ATUC64/128/256L3/4U
show examples of data transfers.
7
CPOL
1
1
0
0
1
1
8
LSB
LSB
***
NCPHA
1
0
1
0
489