ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 944

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.3.4
32142A–12/2011
SCIF
3. Unused PB clocks are running
1. The RC32K output on PA20 is not always permanently disabled
2. PLL lock might not clear after disable
3. PLLCOUNT value larger than zero can cause PLLEN glitch
4. RCSYS is not calibrated
5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
Three unused PBA clocks are enabled by default and will cause increased active power
consumption.
Fix/Workaround
Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register.
The RC32K output on PA20 may sometimes re-appear.
Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
to properly disable it:
- Run the CPU on RCSYS
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.
Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator
may not go back to zero after the PLL oscillator has been disabled. This can cause the prop-
agation of clock signals with the wrong frequency to parts of the system that use the PLL
clock.
Fix/Workaround
PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL
has been turned off, a delay of 30us must be observed after the PLL has been enabled
again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is
locked.
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz
can be expected.
Fix/Workaround
If a known clock source is available the RCSYS can be runtime calibrated by using the fre-
quency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF.
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-
tion in the SCIF memory range.
Fix/Workaround
ATUC64/128/256L3/4U
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