M55800A Atmel Corporation, M55800A Datasheet - Page 120

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

16.9.3
Register Name:
Access Type:
Offset:
Reset Value:
This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or
disabled.
1 = PIO is active on the corresponding line (peripheral is inactive).
0 = PIO is inactive on the corresponding line (peripheral is active).
16.9.4
Register Name:
Access Type:
Offset:
This register is used to enable PIO output drivers. If the pin is driven by a peripheral, this has no effect on the pin, but the
information is stored. The register is programmed as follows:
1 = Enables the PIO output on the corresponding pin.
0 = No effect.
120
P31
P23
P15
P31
P23
P15
31
23
15
P7
31
23
15
P7
7
7
AT91M5880A
PIO Status Register
PIO Output Enable Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_PSR
Read-only
0x08
0x3FFFFFFF (A)
0x0FFFFFFF (B)
6
PIO_OER
Write-only
0x10
6
P29
P21
P13
P29
P21
P13
29
21
13
P5
29
21
13
P5
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
P27
P19
P11
P27
P19
P11
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
1745F–ATARM–06-Sep-07
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0