M55800A Atmel Corporation, M55800A Datasheet - Page 141

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M55800A

Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of M55800A

Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
18.6.2
1745F–ATARM–06-Sep-07
Receive Break
The standard break transmission sequence is:
1. Wait for the transmitter ready
2. Send the STTBRK command
3. Wait for the transmitter ready
4. Send the STPBRK command
The next byte can then be sent:
5. Wait for the transmitter ready
6. Send the next byte
Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR is set.
For character transmission, the USART channel must be enabled before sending a break.
The receiver detects a break condition when all data, parity and stop bits are low. When the low
stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of receive break is
detected by a high level for at least 1-bit + 1/16 of a bit period in asynchronous operating mode
or at least one sample in synchronous operating mode. RXBRK is also asserted when an end of
break is detected.
Both the beginning and the end of a break can be detected by interrupt if the bit
US_IMR.RXBRK is set.
(US_CSR.TXRDY = 1)
(write 0x0200 to US_CR)
(bit TXRDY = 1 in US_CSR)
(write 0x0400 to US_CR)
(bit TXRDY = 1 in US_CSR)
(write byte to US_THR)
AT91M5880A
141

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