M55800A Atmel Corporation, M55800A Datasheet - Page 57

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.3.3
12.3.4
1745F–ATARM–06-Sep-07
PLL Filter
Master Clock Selection
Note:
If the PLL multiplication is changed while the PLL is already active, the LOCK bit in APMC_SR is
automatically cleared and the same sequence is restarted. The PLL is automatically bypassed
while the frequency is changing (while LOCK is 0). If the Main Oscillator is reactivated at the
same time the PLL is enabled, the LOCK bit is set only when both the Main Oscillator and the
PLL are stabilized.
The Phase Lock Loop has a dedicated PLLRC pin which must connect with an appropriate sec-
ond order filter made up of one resistor and two capacitors. If the integrated PLL is not used, it
can remain disabled. The PLLRC pin must be grounded if the resistor and the capacitors need to
be saved. The following figure shows a typical filter connection.
Figure 12-5. Typical Filter Connection
In order to obtain optimal results with a 16 MHz input frequency and a 32 MHz output frequency,
the typical component values for the PLL filter are:
R = 287Ω - C1 = 680 nF - C2 = 68 nF
The lock time with these values is about 3.5 µs in this example.
The MCK (Master Clock) can be selected through the CSS field in APMC_CGMR between the
Slow Clock, the output of the Main Oscillator or the output of the PLL.
The following CSS field definitions are forbidden and the write operations are not taken into
account by the APMC:
This clock switch is performed in some Slow Clocks and PLLs or Main Oscillator clock cycles as
described in the state machine diagram below:
• deselect the Slow Clock if the Main Oscillator is disabled or its output is not stabilized
• disable the PLL without having first selected the Slow Clock or the Main Oscillator clock
• select the PLL clock and, in the same register, write disable the PLL
• select either the Main Oscillator or the PLL clocks and, in the same register, write disable the
• disable the Main Oscillator without having first selected the Slow Clock
Main Oscillator
Programming one in PLLCOUNT is the minimum allowed and guarantees at least 2 Slow Clock
cycles before the lock bit is set. Programming n in PLLCOUNT guarantees (n+1) the delay of Slow
Clock cycles. When the PLL Counter reaches 0, the LOCK bit in APMC_SR is set and can cause
an interrupt. Programming MUL or PLLCOUNT before the LOCK bit is set may lead to unpredict-
able behavior.
GNDPLL
PLLRC
C
R
1
C
2
AT91M5880A
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