M55800A Atmel Corporation, M55800A Datasheet - Page 58

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.3.5
12.3.6
12.3.7
58
AT91M5880A
Slow Clock Interrupt
Prescaler
Master Clock Output
Figure 12-6. Clock Switch
The APMC also features the Slow Clock interrupt, allowing the user to detect when the Master
Clock is actually switched to the Slow Clock. Switching from the Slow Clock to a higher fre-
quency is generally performed safely, as the processor is running slower than the target
frequency. However, switching from a high frequency to the Slow Clock requires the high fre-
quency to be valid during the switch time. The Slow Clock interrupt permits the user to know
exactly when the switch has been achieved, thus, when the Main Oscillator or the PLL can be
disabled.
The prescaler is the last stage to provide the master clock. It permits the selected clock to be
divided by a power of 2 between 1 and 64. The default value is 1 after the reset. The prescaler
allows the microcontroller operating frequency to reach down to 512 Hz.
Precautions must be taken when defining a master clock lower than the Slow Clock, as some
peripherals (RTC and APMC) can still operate at Slow Clock frequency. In this case, access to
the peripheral registers that are updated at 32 kHz cannot be ensured.
The Master Clock can be output to the MCKO pad. The MCKO pad can be tri-stated to minimize
power consumption by setting the bit MCKODS (Master Clock Output Disable) in APMC_CGMR
(default is MCKO enabled).
PLL Clock Mode
3 PLL Clock Cycles
5 SLCK Cycles
7 SLCK Cycles
+
3 PLL Clock Cycles
4 SLCK Cycles
Slow Clock Mode
3 Oscillator Clock Cycles
+
3 PLL Clock Cycles
4 SLCK Cycles
5 SLCK Cycles
+
+
3 Oscillator Clock Cycles
3 SLCK Cycles
+
Oscillator Clock Mode
5 SLCK Cycles
1745F–ATARM–06-Sep-07