M55800A Atmel Corporation, M55800A Datasheet - Page 246

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27. Errata
27.1
27.2
246
ADC: ADC Characteristics and Behavior
Warning: Additional NWAIT Constraints
AT91M5880A
The following known errata are applicable to:
The tracking time has a theoretical minimum duration. It equals one ADC Clock period and is
normally ensured by the ADC Controller.
It might randomly happen that this minimum duration cannot be guaranteed on the first enabled
channel. When this happens, the sampling and hold process is too short and the conversion
result is wrong.
To use only one channel, the user has to enable two channels and then must use the second
channel only.
In the event that all of the ADC channels need to be used, only three channels will be available.
A software work around allows all the channels to be used. It consists of performing several con-
versions and averaging the samples on the first enabled channel. This method does not support
fast conversion. However, signals from temperature sensors, which are slow signals, can be
handled by averaging a number of samples.
• The following datasheets:
• 176-lead LQFP and 176-ball BGA devices with the following markings:
AT91M55800A Summary, 1745S
AT91M55800A, (This document)
AT91M55800A, Electrical Characteristics Rev.1727
Problem Fix/Work Around
When the NWAIT signal is asserted during an external memory access, the following EBI
behavior is correct:
In these cases, the access is delayed as required by NWAIT and the access operations are
correctly performed.
– NWAIT is asserted before the first rising edge of the master clock and respects the
– NWAIT is sampled inactive and at least one standard wait state remains to be
NWAIT to MCKI rising setup timing as defined in the Electrical Characteristics
datasheet.
executed, even if NWAIT does not meet the NWAIT to first MCKI rising setup timing
(i.e., NWAIT is asserted only on the second rising edge of MCKI).
1745F–ATARM–06-Sep-07