M55800A Atmel Corporation, M55800A Datasheet - Page 249

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27.3
27.4
27.5
1745F–ATARM–06-Sep-07
APMC: Unpredictable Result in APMC State Machine on Switch from Oscillator to PLL
APMC: Clock Switching with the Prescaler in the APMC is not Permitted
SPI: Initializing SPI in Master Mode May Cause a Mode Fault Detection
If the first two conditions are not met during write accesses, the NWE signal is not affected by
the NWAIT assertion. The following example illustrates the number of standard wait states.
NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the
standard access. The access is correctly delayed as the NCS line rises accordingly to the
NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
Figure 27-4. Description of the Number of Standard Wait States
An automatic switch from the main oscillator output (CSS = 1) may cause an unpredictable
result in the APMC state machine. The automatic PLL to PLL transition is also effected by this
problem.
The user must either wait for the PLL lock flag to be set in the APMC status register or switch to
an intermediate 32 kHz oscillator output (CSS = 0).
Switching from the selected clock (PRES = 0) to the selected clock divided by 4 (PRES = 2), 8
(PRES = 3) or 64 (PRES = 6) may lead to unpredictable results.
First, the user should switch to any other value (PRES = 1, 4 or 5) and wait for the actual switch
to perform (at least 64 cycles of the selected clock). Then, the user can write the final prescaler
value.
In order to prevent this error, the user must pull up the PA26/NPCS0/NSS pin to the V
supply.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
MCKI
NWAIT
NCS
NWE
Access Length = One Wait State + Assertion of the NWAIT for One More Cycle
EBI
5
AT91M5880A
Erroneous NWE Rising
DDIO
power
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