M55800A Atmel Corporation, M55800A Datasheet - Page 30

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.6
11.6.1
11.6.2
30
Read Protocols
AT91M5880A
Standard Read Protocol
Early Read Protocol
The EBI provides two alternative protocols for external memory read access: standard and early
read. The difference between the two protocols lies in the timing of the NRD (read cycle)
waveform.
The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid for
all memory devices. Standard read protocol is the default protocol after reset.
Note:
Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are
active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address and NCS before the
read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is valid at
the beginning of the access while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict (see
goes low in the second half of the master clock cycle (see
Figure 11-7. Standard Read Protocol
Early read protocol provides more time for a read access from the memory by asserting NRD at
the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuously. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be used.
However, an extra wait state is required in some cases to avoid contentions on the external bus.
In the following waveforms and descriptions, NRD represents NRD and NOE since the two signals
have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless NWR0 and
NWR1 are otherwise represented. ADDR represents A0 - A23 and/or A1 - A23.
or
ADDR
NWE
MCK
NRD
NCS
Figure
11-7). NWE is the same in both protocols. NWE always
Figure
11-8).
1745F–ATARM–06-Sep-07