M55800A Atmel Corporation, M55800A Datasheet - Page 59
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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12.4
12.5
12.6
1745F–ATARM–06-Sep-07
System Clock
Peripheral Clocks
Shut-down and Wake-up
The AT91M55800A has only one system clock: the ARM Core clock. It can be enabled and dis-
abled by writing to the System Clock Enable (APMC_SCER) and System Clock Disable
Registers (APMC_SCDR). The status of the ARM Core clock (at least for debug purposes) can
be read in the System Clock Status Register (APMC_SCSR).
The ARM Core clock is enabled after a reset and is automatically re-enabled by any enabled
interrupt.
When the ARM Core clock is disabled, the current instruction is finished before the clock is
stopped.
Note:
Each peripheral clock integrated in the AT91M55800A can be individually enabled and disabled
by writing to the Peripheral Clock Enable (APMC_PCER) and Peripheral Clock Disable
(APMC_PCDR) Registers. The status of the peripheral clocks can be read in the Peripheral
Clock Status Register (APMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-
enabled, the peripheral resumes action where it left off.
In order to stop a peripheral, it is recommended that the system software waits until the periph-
eral has executed its last programmed operation before disabling the clock. This is to avoid data
corruption or erroneous behavior of the system.
The peripheral clocks are automatically disabled after a reset.
The bits that control the peripheral clocks are the same as those that control the Interrupt
Sources in the AIC.
The APMC (Advanced Power Management Controller) integrates shut-down and wake-up logic
to control an external main power supply. This logic is supplied by the Battery Backup Power.
This feature makes the Power-down mode possible.
If the SHDN pin is connected to the shut-down pin of the main power supply, the Shut-down
command (SHDALC) in APMC_PCR disables the main power. The shut-down input of the con-
verter is generally pulled up or down by a resistor, depending on its active level.
There are 3 ways to exit Power-down mode and restart the main power:
Figure 12-7 shows a typical application using the Shut-down and Wake-up features.
• An alarm programmed in the RTC occurs and the bit ALWKEN in APMC_PMR is set.
• An edge defined by the field WKEDG in APMC_PMR occurs on the pin WAKEUP.
• The user opens the Shut-down line with an external jumper or push-button.
Stopping the ARM Core does not prevent PDC transfers.
AT91M5880A
59
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