M55800A Atmel Corporation, M55800A Datasheet - Page 137
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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18.3
18.3.1
1745F–ATARM–06-Sep-07
Receiver
Asynchronous Receiver
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In
asynchronous mode, the USART detects the start of a received character by sampling the RXD
signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid start bit
if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate.
Hence a space which is longer than 7/16 of the bit period is detected as a valid start bit. A space
which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid
start bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (one bit period)
so the sampling point is 8 cycles (0.5-bit periods) after the start of the bit. The first sampling point
is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each
subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 18-3.
Figure 18-4. Asynchronous Mode: Character Reception
Rate Clock
Example: 8-bit, parity enabled 1 stop
16 x Baud
Sampling
Sampling
RXD
RXD
Asynchronous Mode: Start Bit Detection
periods
0.5-bit
True Start Detection
period
1-bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
AT91M5880A
D7
Parity Bit
Stop Bit
D0
137
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