M55800A Atmel Corporation, M55800A Datasheet - Page 33
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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11.8
11.8.1
11.8.2
1745F–ATARM–06-Sep-07
Wait States
Standard Wait States
Data Float Wait State
The EBI can automatically insert wait states. The different types of wait states are listed below:
Each chip select can be programmed to insert one or more wait states during an access on the
corresponding device. This is done by setting the WSE field in the corresponding EBI_CSR. The
number of cycles to insert is programmed in the NWS field in the same register.
Below is the correspondence between the number of standard wait states programmed and the
number of cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Figure 11-11. One Wait State Access
Notes:
Some memory devices are slow to release the external bus. For such devices it is necessary to
add wait states (data float waits) after a read access before starting a write access or a read
access to a different external memory.
The Data Float Output Time (t
field of the EBI_CSR register for the corresponding chip select. The value (0 - 7 clock cycles)
indicates the number of data float waits to be inserted and represents the time allowed for the
data output to go high impedance after the memory is disabled.
• Standard wait states
• Data float wait states
• External wait states
• Chip select change wait states
• Early read wait states (as described in Read Protocols)
0 wait states
1 wait state
1. Early Read Protocol
2. Standard Read Protocol
ADDR
NWE
MCK
NRD
NCS
DF
(1)
) for each external memory device is programmed in the TDF
1 Wait State Access
1/2 cycle
1 cycle
(2)
AT91M5880A
33
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