M55800A Atmel Corporation, M55800A Datasheet - Page 140

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.6
18.6.1
140
Break
AT91M5880A
Transmit Break
A break condition is a low signal level which has a duration of at least one character (including
start/stop bits and parity).
The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR
(Control Register). In this case, the character present in the Transmit Shift Register is completed
before the line is held low.
To cancel a break condition on the TXD line, the STPBRK command in US_CR must be set. The
USART completes a minimum break duration of one character length. The TXD line then returns
to high level (idle state) for at least 12-bit periods to ensure that the end of break is correctly
detected. Then the transmitter resumes normal operation.
The BREAK is managed like a character:
In order to avoid unpredictable states:
• The STTBRK and the STPBRK commands are performed only if the transmitter is ready (bit
• The STTBRK command blocks the transmitter holding register (bit TXRDY is cleared in
• A break is started when the Shift Register is empty (any previous character is fully
• STTBRK and STPBRK commands must not be requested at the same time
• Once an STTBRK command is requested, further STTBRK commands are ignored until the
• All STPBRK commands requested without a previous STTBRK command are ignored
• A byte written into the Transmit Holding Register while a break is pending but not started (bit
• It is not permitted to write new data in the Transmit Holding Register while a break is in
• A new STTBRK command must not be issued until an existing break has ended
TXRDY = 1 in US_CSR)
US_CSR) until the break has started
transmitted). US_CSR.TXEMPTY is cleared. The break blocks the transmitter shift register
until it is completed (high level for at least 12-bit periods after the STPBRK command is
requested)
BREAK is ended (high level for at least 12-bit periods)
TXRDY = 0 in US_CSR) is ignored
progress (STPBRK has not been requested), even though TXRDY = 1 in US_CSR.
(TXEMPTY=1 in US_CSR).
1745F–ATARM–06-Sep-07