SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 208

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.4
23.4.1
208
Product Dependencies
AT91SAM9R64/RL64
SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
After initialization, the SDRAM devices are fully functional.
Note:
1. SDRAM features must be set in the configuration register: asynchronous timings (TRC,
2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength
3. The SDRAM memory type must be set in the Memory Device Register.
4. A minimum pause of 200 µs is provided to precede any signal toggle.
5.
6. An All Banks Precharge command is issued to the SDRAM devices. The application
7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in
8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is
10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and
11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register.
TRAS, etc.), number of columns, rows, CAS latency, and the data bus width.
(DS) and partial array self refresh (PASR) must be set in the Low Power Register.
(1)
1 in the Mode Register and perform a write access to any SDRAM address.
must set Mode to 2 in the Mode Register and perform a write access to any SDRAM
address.
the Mode Register and perform a write access to any SDRAM location eight times.
devices, in particular CAS latency and burst length. The application must set Mode to 3
in the Mode Register and perform a write access to the SDRAM. The write address
must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
issued to program the SDRAM parameters (TCSR, PASR, DS). The application must
set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The
write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a
16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write
access should be done at the address 0x20800000 or 0x20400000.
performing a write access at any location in the SDRAM.
(Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh
every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter
Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100
MHz).
A NOP command is issued to the SDRAM devices. The application must set Mode to
1. It is strongly recommended to respect the instructions stated in
cess in order to be certain that the subsequent commands issued by the SDRAMC will be
taken into account.
Step 5
of the initialization pro-
6289D–ATARM–3-Oct-11