SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 624
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 624 of 903
- Download datasheet (13Mb)
38.7.3
624
AT91SAM9R64/RL64
Read Operation
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
The following flowchart shows how to read a single block with or without use of PDC facilities. In
this example (see
the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end
of read.
• Open-ended/Infinite Multiple block read (or write):
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The number of blocks for the read (or write) multiple block operation is not defined. The card
continuously transfers (or programs) data blocks until a stop transmission command is
received.
The card transfers (or programs) the requested number of data blocks and terminate the
transaction. The stop command is not required at the end of this type of multiple block read
(or write), unless terminated with an error. In order to start a multiple block read (or write)
with pre-defined block count, the host must correctly program the MCI Block Register
(MCI_BLKR). Otherwise the card starts an open-ended multiple block read. The BCNT field
of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Pro-
gramming the value 0 in the BCNT field corresponds to an infinite block transfer.
Figure
38-10), a polling method is used to wait for the end of read. Similarly,
6289D–ATARM–3-Oct-11
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