SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 721
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 721 of 903
- Download datasheet (13Mb)
40.7.1
Name:
Access Type:
• VRA: Variable Rate (for Data Slots 3-12)
0: Variable Rate is inactive. (48 KHz only)
1: Variable Rate is active.
• WRST: Warm Reset
0: Warm Reset is inactive.
1: Warm Reset is active.
• ENA: AC’97 Controller Global Enable
0: No effect. AC’97 function as well as access to other AC’97 Controller registers are disabled.
1: Activates the AC’97 function.
40.7.2
Register Name:
Access Type:
• CHIDx: Channel ID for the input slot x
6289D–ATARM–3-Oct-11
CHID8
31
23
15
31
23
15
–
–
–
7
–
–
7
CHIDx
AC’97 Controller Mode Register
AC’97 Controller Input Channel Assignment Register
0x0
0x1
0x2
CHID5
CHID10
30
22
14
30
22
14
AC97C_MR
Read-Write
–
–
–
6
–
AC97C_ICA
Read/Write
–
6
Selected Receive Channel
None. No data will be received during this Slot x
Channel A data will be received during this slot time.
Channel B data will be received during this slot time
CHID7
29
21
13
29
21
13
–
–
–
5
–
5
CHID12
CHID4
28
20
12
28
20
12
–
–
–
4
–
4
CHID9
27
19
11
27
19
11
–
–
–
3
–
3
CHID6
VRA
AT91SAM9R64/RL64
26
18
10
26
18
10
–
–
–
2
2
CHID11
WRST
CHID3
25
17
25
17
–
–
9
–
1
9
1
CHID8
CHID5
ENA
24
16
24
16
–
–
8
–
0
8
0
721
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